SPSB100 datasheet(48/213 Pages) STMICROELECTRONICS

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Any further voltage attachment to SWDBG pin at VIO is ignored, until the next SPSB100 power-up sequence.

This helps to protect unwanted SW-Debug mode entry and well enables possible share of this pin with other

functions.

Once the SW-Debug mode is established, it persists until terminated via SPI command SWDBG_EXIT or until the

next power on reset (battery unplug and replug). If terminated by SPI command the watchdog starts immediately

with a long open window.

The SW-Debug mode status can be monitored by the SPI status register WD_ENA_ECHO = 0.

The state of the SWDBG pin can be monitored by the live bit SWDBG_STATE.

In final application, it is possible to detect the hardware fault “SWDBG shorted to VIO” using the following

procedure.

After the MCU boot-up, the software shall read the SPSB100 state. The expected state is REC-1. If the SWDBG

pin is faulty shorted to VIO then the device reaches SWDBG state.

In such a case it is possible to kill the timeout by setting the KILL_SWDBG_TIMEOUT control bit: the device

transits to REC-1 state and the watchdog is enabled disregarding the SWDBG pin voltage.

This feature is useful to prevent an increase of start-up time when the hardware fault “SWDBG shorted to VIO” is

present.

3.18

VREG

The VREG is dedicated to generate the bootstrap voltage for the BUCKs in active and REC-1 states. It is supplied

by FBB pin in active-full power and by FB1 in active-low power.

VREG has a 3.3 V output and 150 mA current capability.

VREG cannot be used to supply external blocks.

The voltage regulator is protected against undervoltage: if the VREG output voltage is going below VVREG_UV for

a delay higher than tVREG_UV, flag INT_REG_UV is set and the device will execute a power down sequence to

enter in DEEP-SLEEP state.

The voltage regulator is protected against overvoltage: if the VREG output voltage is going above VVREG_OV for a

delay higher than tVREG_OV, flag INT_REG_OV is set and the device will execute a power down sequence to

enter in DEEP-SLEEP state.

The voltage regulator is protected against a short to ground during INIT state. If the VREG output voltage is not

able to reach VVREG_UV after tVREG_stup, flag INT_REG_UV is set and the device will make a transition to DEEP-

SLEEP state.

Current limitation IVREG_CCmax of the regulator ensures fast charge of external decoupling capacitor.

The output voltage is stable for ceramic load capacitors, see CVREG in the Section 7.22: VREG voltage regulator.

Warning temperature detection is managed by a local thermal sensor (flag is TW_CL0).

Warning temperature detection generates an IRQ except if MASK_CL0_TW_IRQ is set.

In case the device temperature exceeds the TSD_CL0 threshold, the device executes a power down sequence

before entering in REC-2 state.

SPSB100

Functional description

DS14640 - Rev 2

page 48/213

SPSB100 Datenblatt(PDF) 48 Page - STMicroelectronics