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SPSB100 Datenblatt(PDF) 62 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 62 Page - STMicroelectronics |
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62 / 213 page ![]() RAM address Description Access 04H <Device No.3> R 03H <Device No.2> R 02H <Device No.1> R 01H <Device Family> R 00H <Company Code> R 5.2.3.1 Device information registers The device information registers can be read by using OpCode ‘11’. After shifting out the GSB the 8bit wide payload will be transmitted. By reading device information registers a communication width which is minimum 16 bits can be used. After shifting out the GSB followed by the 8bit wide payload a series of ‘0’ is shifted out at the SDO. Table 15. Information registers map ROM address Description Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 … 3EH <GSB Options> R 0 0 0 0 0 0 0 0 … 20H <SPI CPHA test> R 0 1 0 1 0 1 0 1 … 15H <WD bit pos. 3> R 00H 14H <WD bit pos. 2> R C0H 13H <WD bit pos. 1> R 44H 12H <WD Type 2> R 91H 11H <WD Type 1> R Watchdog long open window (refers to watchdog definition) 10H <SPI mode> R 32H … 0AH <Silicon Ver.> R Major revision Minor revision … 06H <Device No.5> R 01H: SPSB100B and SPSB100P 05H <Device No.4> R 4EH 04H <Device No.3> R 38H 03H <Device No.2> R 52H 02H <Device No.1> R 55H 01H <Device Family> R 01H 00H <Company Code> R 00H 5.2.3.1.1 Device identification registers These registers represent a unique signature to identify the device and silicon version. <Company Code>: 00H (STMicroelectronics) <Device Family>: 01H (BCD power management) <Device No. 1>: 55H (ASCII code for U) <Device No. 2>: 52H (ASCII code for R) <Device No. 3>: 38H (ASCII code for 8) SPSB100 Serial peripheral interface (SPI) DS14640 - Rev 2 page 62/213 |
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