SPSB100 datasheet(33/213 Pages) STMICROELECTRONICS

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To transit to LOW-POWER mode the following sequence must be played by the MCU:

•

Assert low NFSO1 output (optional).

•

Reconfigure watchdog timing (optional).

•

Disable the watchdog by setting WD_LP_ENA = 0 (optional).

•

Turn off the FCCU monitoring feature.

•

Turn OFF regulators BUCK3 and LDO2.

•

BUCK1 and/or BUCK2 can be kept ON if one of it is used to supply VIO.

•

Configure wake-up sources and IRQ generation (optional).

Until this step, the SPSB100 is still in FULL-POWER mode, but with tuned settings.

•

Set to 1 SPI bit LOW_POWER_SET (only after SPI_PROTECT_ACCESS has been set).

This last action sets SPSB100 in LOW-POWER mode, SPSB100 generates an interruption to confirm the proper

entrance in LOW-POWER mode (except if MASK_LP_READY_IRQ is set) and sets status bit LP_READY.

To transit from LOW-POWER to FULL-POWER mode the following sequence must be played by the MCU:

•

Clear to 0 SPI bit LOW_POWER_SET (only after SPI_PROTECT_ACCESS has been set).

This first action sets SPSB100 in FULL-POWER mode, SPSB100 generates an interruption to confirm the proper

entrance in FULL-POWER mode and sets status bit FP_READY. MCU must wait for this confirmation before

continuing, then:

•

Clear low power setting of regulator(s) 1 and/or 2 kept ON before its/their load current increases.

•

Turn ON other regulator(s) as per application needs.

•

Reconfigure watchdog timing to satisfy functional safety requirements (optional).

•

Turn ON the FCCU monitoring feature.

•

Trigger watchdog during LOW if WD_LP_ENA = 0 (optional).

•

Configure wake-up sources and IRQ generation (optional).

•

Deassert NFSO1 output.

The low-level hardware monitoring is turned back ON when SPI bit LOW_POWER_SET is cleared. If a hardware

fault is detected, SPSB100 transits asynchronously to DEEP-SLEEP state.

LOW_POWER_SET, FP_READY and LP_READY are not automatically cleared in case of transition due to hard

fail.

3.6.3.6

RECOVERY-1 state

SPSB100 enters in RECOVERY-1 state in two cases:

•

From INIT state after the power-up sequence ended successfully.

•

From ACTIVE state after a WD trigger issue or a FCCU fault is detected.

When entering the RECOVERY-1 state:

•

NFSO1 output is asserted low.

•

FCCU monitoring is turned OFF.

•

WD starts a LOW, except if LOW_SET = 1111.

In this state all voltage regulators are set according to the power-up sequence settings stored in USER-NVM. If

some of the voltage regulators configured in the power-up sequence were switched off in ACTIVE state through

the SPI, they are enabled upon entering in RECOVERY-1 state.

The transition from RECOVERY-1 to ACTIVE state is started after the MCU has read and cleared error flags (if

any, see the Section 9.8: Status register that must be cleared to enter into active FP mode) and trigged the WD in

LOW.

In RECOVERY-1 state, the MCU cannot deassert NFSO1 output. A further WD trigger fault generates a NRST

low pulse of at least 4 ms long. See the Section 3.10: Configurable time-out window watchdog for further details.

If FCCU is enabled by MCU and a FCCU fault is detected then SPSB100 remains in RECOVERY-1 state and

generates a NRST low pulse of at least 6 ms long. See the Section 3.11: FIN1 input for details.

3.6.3.7

RECOVERY-2 state

SPSB100 enters in RECOVERY-2 state from ACTIVE state and generates status register bit FSM_TO_REC2 = 0

in case of:

•

DO_POWER_CYCLE SPI command (only after SPI_PROTECT_ACCESS has been set).

•

The temperature of the central sensor overpassed the TSDC threshold.

SPSB100

Functional description

DS14640 - Rev 2

page 33/213

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