SPSB100 datasheet(56/213 Pages) STMICROELECTRONICS

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Serial peripheral interface (SPI)

A 32-bit SPI is used for bidirectional communication with the microcontroller.

The microcontroller SPI peripheral shall be configured with CPOL = 0 and CPHA = 0: SDI input data is sampled

by the rising CLK edge, and SDO output data is updated on the falling CLK edge.

This device is not limited to microcontroller with a built-in SPI peripheral, instead three CMOS-compatible output

pins and one input pin may be used to communicate with the device. A fault condition can be detected by setting

CSN to low, in such condition the SDO pin reflects the global error flag GSBN of the device.

•

Chip select not (CSN)

The CSN input pin is used to select the serial interface of this device. When CSN is high, the output pin

SDO is in a high impedance state. CSN low activates the output driver and a serial communication can be

started. The state during CSN = 0 is called a communication frame. If CSN is low for t > tCSNfail the SDO

output will be switched back to high impedance not to block the signal line for other SPI nodes.

•

Serial data in (SDI)

The SDI input pin is used to transfer data into the device. The data applied to SDI are sampled at the rising

edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal

the content of the shift register is transferred to the data input register. The writing to the selected data

input register is enabled if exactly 32 bits are transmitted within one communication frame (that is, CSN

low). If more or less clock pulses are counted within one frame the complete frame is ignored and a SPI

error is signaled. This safety function is implemented to avoid an activation of the output stages by a wrong

communication frame. Due to this safety functionality, a daisy chaining of SPI is not possible. Instead, a

parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.

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Serial data out (SDO)

The data output driver is activated by a logical low level at the CSN input and will go from high impedance

to a low or high level depending on the global error flag GSBN. The first rising edge of the CLK input after a

high to low transition of the CSN pin transfers the content of the selected status register into the data out

shift register. Each subsequent falling edge of the CLK will shift the next bit out. As SDO is in high

impedance when CSN is high, it is possible to link several SPI target devices that respect this rule with a

dedicated CSN line for each SPI target.

•

Serial Clock (CLK)

The CLK input is used to synchronize the input and output bit streams. The data input (SDI) is sampled at

the rising edge of the CLK and the data output SDO is updated on the falling edge of the CLK signal.

5.1

ST-SPI

The ST-SPI is a standard used in ST automotive ASSP devices.

This chapter describes the SPI protocol. It defines a common structure of the communication frames and defines

specific addresses for product and status information.

The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to

adapt it to the individual functionality of a particular product. In addition, safety mechanisms are implemented to

protect the communication from external influences and wrong or unwanted usage.

SPSB100

Serial peripheral interface (SPI)

DS14640 - Rev 2

page 56/213

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