SPSB100 datasheet(55/213 Pages) STMICROELECTRONICS

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LBIST2 must be run only in Active-Full power mode by MCU through the SPI. MCU shall write LBIST bit to

request its execution (only after SPI_PROTECT_ACCESS has been set). The LBIST2 execution is delayed until

the NVM controller terminates its self-test

After tLBIST, the LBIST2 is finished, the status bit LBIST_COMPLETE is set and an interrupt is sent to IRQ pin.

LBIST_ERROR_1 is set in case a LBIST2 error is detected.

SPSB100 does not take any action in case of an LBIST2 error is detected. It is the duty of the MCU to proper

react on such a signaled error.

LBIST error detected in INIT state is considered as a safety check error (see the Section 4.17: Safety checks).

Fault management while LBIST is executed:

•

When LBIST1 and LBIST2 are executed in INIT state the internal faults processed by the blocks under

LBIST are masked, their processing by SPSB100 is delayed until the end of LBIST1 & LBIST2.

•

When LBIST2 is executed on demand in active-full power mode the faults (UV, OV, TSD…) processed by

the blocks under LBIST2 are not masked. If a fault occurs the LBIST2 is stopped, status bit

LBIST_STOPPED is set and an IRQ is generated, the fault is processed by SPSB100 with appropriate

reaction.

•

As a consequence the watchdog window must be properly set before requesting a LBIST2 execution to let

the LBIST2 complete before the next watchdog trig through SPI.

4.17

Safety checks

Safety checks are executed in INIT state. They are made of:

•

Digital BIST LBIST1 and LBIST2.

•

Ground pin monitor.

•

NVM checks: CRC and U-PROG value.

In case of error the state machine transits to DEEP-SLEEP where the device can be woken up to INIT state

where safety checks are run again.

4.18

NVM integrity monitor

To detect an improper turn-OFF of NVM monitor feature, the device embeds an echo signal of the NVM monitor

block enable signal: NVM_COMPARE_ENA_STATUS live bit in the status register. This status bit is set if a fault

disables the comparison of NVM data with redundant registers, in such case an interrupt is sent to IRQ pin. The

reaction of the NVM monitor features in case of error is described in the Section 4.8: HW low-level monitors.

SPSB100

Protection, diagnosis and monitoring signals

DS14640 - Rev 2

page 55/213

SPSB100 Datenblatt(PDF) 55 Page - STMicroelectronics