SPSB100 datasheet(36/213 Pages) STMICROELECTRONICS

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If this option is selected, then the device waits for the PG signal of all turned ON regulators at step N. A

time-out is used to detect a fault: if the time-out expires a power-down sequence is executed and a retry

procedure is started as described in the Section 3.6.2.3: Power-up fault management.

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If not, or when PG level is reached, the sequence is paused for a programmable delay with USER-NVM

bits PU_WAIT_DEL_ENA_X (X equal to steps from 1 to 7) before proceeding to the next step.

While the sequence executes, any regulator fault is managed as per its REGFAIL_GO_REC setting as described

in the Section 3.6.2.5: Regulator faults management.

3.7.2

Power-down sequence

Power-down sequence is made of 7 steps as described below.

Figure 23. Power-down sequence

Step #N:

Turn OFF regulators & assert NRESET if their

PD_STEP_OFF (resp PD_STEP_ASSERT ) = N,

no action on others.

Turn OFF WD,

Set N=1

Wait for

PD_WAIT_DEL_OFF <N> ms

Set N = N + 1

N ≥ 8 ?

Finished

Start

End

Turn OFF BOOST and internal VREG

regulator

Wait PD_WAIT_VREG_DEL_OFF ms,

Each of BUCK-1, -2, -3, and LDO-1, -2 can be turned OFF with USER-NVM bits BUCK1_PD_STEP_OFF,

BUCK2_PD_STEP_OFF, BUCK3_PD_STEP_OFF, LDO1_PD_STEP_OFF, LDO2_PD_STEP_OFF at any step

from 1 to 7. None, or more than one regulator can be turned OFF at a step.

The NRST pin can be asserted at any step from 1 to 7 with USER-NVM bits NRESET_PD_STEP_ASSERT,

independently of regulators setting. Note that the watchdog is stopped before step 1.

After a regulator has been turned OFF at step N the sequence offers the possibility to wait for programmable

delay with USER-NVM bits PD_WAIT_DEL_OFF_X (X equal to steps from 1 to 7).

When the sequence ends, an extra delay can be programmed before turning OFF the BOOST and internal VREG

with USER-NVM bits PD_WAIT_VREG_DEL_OFF.

SPSB100

Functional description

DS14640 - Rev 2

page 36/213

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