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SPSB100 Datenblatt(PDF) 61 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 61 Page - STMicroelectronics |
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61 / 213 page ![]() 5.2.3 Address definition Table 12. RAM and ROM address range Operation code OC1 OC0 Description 0 0 Write operation, allowed to RAM control registers 0 1 Read operation, allowed to RAM status or control registers 1 0 Read and clear operation, allowed to RAM status registers 1 1 Read device information in ROM registers Table 13. RAM address RAM address Description Access 3FH Special OpCode R/W … - - 32H Status register 18 R/C … … - 22H Status register 2 R/C 21H Status register 1 R/C … … - 1CH Control register 28 R/W … … - 02H Control register 2 R/W 01H Control register 1 R/W 00H Reserved - Table 14. ROM address RAM address Description Access … - - 3EH <GSB Options> R … - - 20H <SPI CPHA test> R … - - 15H <WD bit pos. 3> R 14H <WD bit pos. 2> R 13H <WD bit pos. 1> R 12H <WD Type 2> R 11H <WD Type 1> R 10H <SPI mode> R … - - 0AH <Silicon Ver.> R … - - 05H <Device No.4> R SPSB100 Serial peripheral interface (SPI) DS14640 - Rev 2 page 61/213 |
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