SPSB100 datasheet(57/213 Pages) STMICROELECTRONICS

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5.1.1

Physical Layer

Figure 32. SPI pin description

CSN

SCK

SDI

SDO

SPSB100

SPI

μC

5.2

Signal description

Chip select not (CSN)

The communication interface is deselected when this input signal is logically high. A falling edge on CSN enables

and starts the communication while a rising edge finishes the communication and the sent command is executed

when a valid frame was sent. At CSN falling and rising edges the serial clock (CLK) has to be logically low. The

serial data out (SDO) is in high impedance when CSN is high or a communication timeout is detected.

Serial clock (CLK)

CLK provides the clock of the SPI. Data present at serial data input (SDI) is latched on the rising edge of serial

clock (CLK) into the internal shift registers while on the falling edge data from the internal shift registers are

shifted out to serial data out (SDO).

Serial data input (SDI)

This input is used to transfer data serially into the device. Data is latched on the rising edge of the serial clock

(CLK).

Serial data output (SDO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the

serial clock (CLK).

5.2.1

Clock and data characteristics

The ST-SPI can be driven by a microcontroller with its SPI peripheral running in the following modes:

•

CPOL = 0

•

CPHA = 0

SPSB100

Serial peripheral interface (SPI)

DS14640 - Rev 2

page 57/213

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