SPSB100 datasheet(13/213 Pages) STMICROELECTRONICS

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3.1.2

System supply configuration 2

Figure 6. Configuration 2: direct supply of the microcontroller core by internal SMPS

SR6P7

BUCK1

BUCK3

LDO1

5 V

3.3V

5.0V

SPI

SPSB100P

VIO

VDD_HV_ADR

SPI Communication*

BUCK2

5.0V

LDO2

*System Configuration for SPI or HV_IO of the MCU, could be selected by customer at 3.3V or 5.0V based on application need (H V_IO and SPI must be at same logic level)

Battery

ADC

CORE

SPI

I/O

NVM

VDD_LV

BOOST

SMPS

VDD_UV_SMPS

Ext. load

Filter

VDD_HV_ADV

VDD_HV* +VDD_HV_IO* + VDD_HV_NVM

3.3V

Ext.

In configuration 2, BUCK1 is configured to provide a 5 V to supply the SMPS of microcontroller that will manage

internally the supply of the core with a switching frequency of 400 kHz. BUCK2 and BUCK3 supply respectively

the 5 V and the 3.3 V rails with a switching frequency of 400 kHz and 2.4 MHz respectively. BUCK3 is supplied by

BUCK2, while the boost supplies BUCK1 and 2 and LDO1 and LDO2, providing 5 V and 3.3 V respectively for

external loads.

The power-up and power-down sequences associated to such supply configuration are the following:

Power-up sequence

1. Turn ON BUCK1 at 5 V, wait PG (BUCK1_PG_OK flag);

2. Turn ON BUCK2 at 5 V, wait PG (BUCK2_PG_OK flag);

3. Turn ON BUCK3 at 3.3 V, wait PG;

4. Deassert NRST, wait 0 ms;

5. Turn ON LDO2 in tracker of BUCK3, wait 0 ms;

6. Turn ON LDO1, wait PG (LDO1_PG_OK flag).

Power-down sequence

1. Turn OFF LDO1, wait 0 ms;

2. Turn OFF LDO2, wait 0 ms;

3. Assert NRST, wait 2 ms;

4. Turn OFF BUCK3, wait 2 ms;

5. Turn OFF BUCK2, wait 2 ms;

6. Turn OFF BUCK1, wait 0 ms;

7. Turn OFF VREG after 10 ms.

Note:

The SR6P7 does not embed LP domain, anyway when the SPI is supplied by BUCK3 at 3.3 V it is not possible

to use SPSB100P in low power mode otherwise SPI will be not supplied and it cannot be possible to

communicate with MCU. The only way to use SPSB100P in low power mode is when both SPI and VDD_HV_IO

are supplied by 5 V through BUCK1 set at 5 V and only in this case, it could be possible to use SPSB100P in

low power mode allowing SPI communication.

3.1.3

Digital interface supply: VIO

VIO pin supplies the SPI interface, and pins IRQ, FIN1, NRST, RxD_C, TxD_C.

VIO can be supplied from one of SPSB100’s BUCK, or from an external regulator.

Digital pins functionalities are guaranteed when VIO > VVIO_UV_R (VIO_UV flag not raised).

SPSB100

Functional description

DS14640 - Rev 2

page 13/213

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