SPSB100 datasheet(32/213 Pages) STMICROELECTRONICS

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•

From RECOVERY-2 state when:

–

MCU sent a SPI command DO_POWER_CYCLE (only after SPI_PROTECT_ACCESS has been set)

in ACTIVE or RECOVERY-1 state.

–

FBB pin voltage is below VFBB_UV_F and VS pin voltage above VPORVS_F.

–

One thermal sensor detected a TSD event, the chip temperature cooled down and the TSD counter

does not reached 3.

–

A fault has been detected on a critical regulator output voltage (REGFAIL_GO_REC = 1).

–

8 successive watchdog trigger faults have been detected

•

In case a fault has been detected during the power-up sequence and the power-up retry counter does not

reach 3, or LOOP_FOR_EVER bit is set to 1.

In INIT state, when FBB pin voltage rises above VFBB_OK_R (the minimum voltage allowing SPSB100 to

power

‑up), SPSB100 executes the digital BIST before initiating a power-up sequence.

3.6.3.5

ACTIVE state

ACTIVE state is the state reached after a successful power-up sequence, after the MCU did a read and clear of

SPI error flags in RECOVERY-1 state and trig the watchdog in long open window timeout.

In ACTIVE state the SPSB100 can be configured in FULL- or LOW- POWER modes.

In both modes the MCU can configure the watchdog timings and control NFSO1 pin through SPI.

Reactions to fault detection are independent of the POWER modes.

3.6.3.5.1

FULL-POWER mode

FULL-POWER mode is the default mode when entering ACTIVE state from RECOVERY-1 state.

In FULL-POWER mode, all features of SPSB100 are accessible and configurable by SPI registers, in particular

MCU can switch OFF some regulators to optimize ECU power consumption.

In FULL-POWER mode, regulator monitors are active and analog and digital BIST can be run on demand by the

MCU. Watchdog is running and must be served, except if LOW_SET = 1111. NFSO1 pin is controllable by SPI

3.6.3.5.2

LOW-POWER mode

LOW-POWER mode is accessible by SPI in ACTIVE state from FULL-POWER mode. In this mode the SPSB100

power consumption is reduced by:

•

Turning OFF low-level hardware monitors.

•

Turning OFF the redundant voltage and current bias blocks.

•

Turning OFF NVM runtime checks.

•

Turning OFF the ADC.

•

Analog and digital BIST shall not be executed on demand.

In LOW-POWER mode:

•

The watchdog is running and must be served (except if WD_LP_ENA is set at 0), its timing is configurable

to further reduce power consumption.

•

Central thermal monitoring is active,

•

If BUCK 1 and/or BUCK 2 and/or LDO 1 is/are kept ON in its/their low power setting then OV and UV

monitoring are active (see the Section 3.8: User's NVM modification procedure for functional safety details).

•

Other regulators must be turned OFF before entering in LOW-POWER mode,

MCU can decide to leave this mode by SPI command and return to FULL-POWER mode.

In LOW-POWER mode the VIO must be supplied and SPSB100 offers three possibilities:

•

All regulators are turned OFF: in this case VIO must be supplied by an external regulator.

•

Only BUCK1 is kept ON in its low-power configuration. BUCK1, or an external regulator, is used to supply

VIO.

•

BUCK1 and 2 are kept ON in their low-power configuration. BUCK1 or 2, or an external regulator, are used

to supply VIO.

3.6.3.5.3

Transitions between FULL-POWER and LOW-POWER modes

Transitions between the two modes are under the responsibility of the MCU.

SPSB100

Functional description

DS14640 - Rev 2

page 32/213

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