SPSB100 datasheet(53/213 Pages) STMICROELECTRONICS

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CLK phase check: To verify that the CLK phase of the SPI controller is set correctly a special device

information register is implemented. By reading this register the data must be 55H. In case AAH is read the

CPHA setting of the SPI controller is wrong and a proper communication cannot be guaranteed.

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CSN timeout: if CSN is set low for t > tCSN fail then the frame is rejected and SDO is released to tri-state

(SPI_CSN_TIMEOUT is set). An IRQ is generated except if MASK_SPI_ERROR_IRQ is set.

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SDI stuck at high detection: an SPI frame consisting of all bits ‘1’ is detected as failure and will be rejected,

SPI_SDI_STUCK_HIGH is set and an IRQ is generated except if MASK_SPI_ERROR_IRQ is set.

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SDI stuck at low detection: an SPI frame consisting of all bits ‘0’ is detected as failure and will be rejected,

SPI_SDI_STUCK_LOW is set and an IRQ is generated except if MASK_SPI_ERROR_IRQ is set.

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SDO stuck: the global status byte (GSB) is transmitted within every SPI frame; the definition of the GSB

guarantees that a content of all ‘1’ or all ‘0’ is not possible; therefore, the microcontroller can identify if the

SDO signal is stuck at high or low level.

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Functional safety relevant configuration registers are locked by a dedicated bit SPI_PROTECT_ACCESS.

A first SPI command must be sent to unprotect the functional safety relevant registers, then a successive

SPI command is sent to modify those configuration registers.

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SPI undefined address access is detected by a dedicated bit SPI_UNDEF_ADD. An IRQ is generated

except if MASK_SPI_ERROR_IRQ is set.

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SPI unwanted write access on a status register is detected by a dedicated bit SPI_STATUS_WRT. An IRQ

is generated except if MASK_SPI_ERROR_IRQ is set.

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SPI unwanted access during LBIST test is detected and SPI_LBISTED is set. An IRQ is generated except

if MASK_SPI_ERROR_IRQ is set. In this case, the SPI frame is rejected.

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Functional safety relevant configuration registers are duplicated and a runtime comparison mechanism

check the coherency of their data. In case of error the reaction is described in the Section 4.8: HW low-

level monitors.

Latent fault detection of SPI digital handler, functional safety redundant configuration register and comparison

mechanism are covered by a Digital-BIST.

4.10

IRQ pin monitoring

To check that the IRQ line is properly connected to the MCU, an IRQ can be sent to the MCU through SPI

request.

When MCU sets the SPI bit IRQ_REQUEST, an interrupt is generated on IRQ pin.

The MCU can verify that the IRQ has well been sent by checking the IRQ_SENT status bit. Pin IRQ shall be set

high after read and clear of IRQ_SENT flag.

To detect IRQ stuck high fault, the device embeds:

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An echo signal of the IRQ pin: IRQ_ECHO live bit in the status register.

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An echo error detection mechanism: IRQ_ECHO_ERROR status bit is set if the device detects an

IRQ_ECHO high signal when IRQ pin is asserted low after a filter time TIRQ_ECHO_FILT.

4.11

NRST pin monitoring

To detect NRST stuck high fault, the device embeds:

•

An echo signal of the NRST pin: NRST_ECHO live bit in the status register.

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An echo error detection mechanism: NRST_ECHO_ERROR status bit is set if the device detects an

NRST_ECHO high signal when NRST pin is asserted low after a filter time TNRST_ECHO_FILT.

4.12

NFSO1 pin monitoring

To detect NFSO1 stuck high fault, the device embeds:

•

An echo signal of the NFSO1 pin: NFSO1_ECHO live bit in status register.

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An echo error detection mechanism: NFSO1_ECHO_ERROR status bit is set if the device detects an

NFSO1_ECHO high signal when NFSO1 pin is asserted low, after a filter time TNFSO_ECHO_FILT and an

interrupt is sent to IRQ pin, except if MASK_NFSO1_ECHO_ERROR_IRQ is set.

4.13

Watchdog block monitoring

To detect an improper turn-OFF of the watchdog feature, the device embeds:

SPSB100

Protection, diagnosis and monitoring signals

DS14640 - Rev 2

page 53/213

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