SPSB100 datasheet(52/213 Pages) STMICROELECTRONICS

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4.8

HW low-level monitors

The SPSB100 integrates asynchronous monitors of low-level blocks in ACTIVE-FULL-POWER mode and REC-1

states:

•

Voltage difference between main and monitoring digital and analog power supplies (INT_REG_UV,

INT_REG_OV bits).

•

Current difference between main and monitoring current sources (CURRENT_MISMATCH bit).

and synchronous monitors of:

•

Frequency difference between main and redundant oscillators (OSC_ERROR bit).

•

State machine’s state by comparison of main and redundant State machine(FSM_COMP_ERROR bit).

•

NVM data by:

–

Comparison of NVM data and redundant registers (NVM_COMP_ERROR bit).

–

CRC check at NVM download(NVM_CRC_ERROR bit).

•

Safety critical SPI registers by comparison of main and redundant registers (SPI_REG_COMP_ERROR bit

generates an IRQ except if MASK_SPI_ERROR_IRQ is set).

•

Ground loss connection by cross-checking ground domains(GNDLOSS bit).

A fault detected by low-level monitors trigs a power-down sequence and SPSB100 reaches the DEEP-SLEEP

state. In such situation, after a wake-up event (except for OSC_ERROR where SPSB100 restarts automatically if

oscillators recover their frequencies), all SPI registers are reset except HW low-level monitor flags and SPSB100

transit to START-SM state.

Figure 30. HW low level monitors

HW monitor errors are:

4.9

Communication interface

The SPI communication protocol embeds the following safety mechanisms:

•

A 4-bit CRC SPI_CRC_ERR is set in case of error detected, and an IRQ is generated except if

MASK_SPI_ERROR_IRQ is set.

•

Clock monitor: during communication (CSN low phase) a clock monitor counts the valid CLK edges. If the

CLK edges do not correlate with the SPI data length then SPI_CLK_CNT is set, an IRQ is generated

except if MASK_SPI_ERROR_IRQ is set, the actual communication is rejected.

SPSB100

Protection, diagnosis and monitoring signals

DS14640 - Rev 2

page 52/213

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