SPSB100 datasheet(26/213 Pages) STMICROELECTRONICS

26 / 213 page

Figure 15. State machine details on power-up fault (2)

DEEP-SLEEP

state

Wake-up

event

REC-1

state

Execute

Power-Up

sequence

Finished OK

INIT

state

Execute

Power-Down

sequence

(retry ≤ 3)

OR (for_ever = 1) ?

Retry loop

NFSO asserted

Execute

Power-Up

sequence

but NRESET not

deasserted

ACTIVE

state

WD trigger OK*

LOW-POWER

mode

FULL-POWER

mode

SPI cmd

WD trigger OK*

(WD trigger fail)*

OR FCCU fail

REC-1

state

PG_TimeOut reached

OR REGfail & GoREC=1

PG_TimeOut reached

OR REGfail & GoREC=1

NRESET asserted

4ms for WD fail or

6ms for FCCU fail,

then WD restarted

in L.O.W.*

NFSO &

NRESET

asserted,

FCCU

disabled

VFBB_OK_R < VFBB < VFBB_OV

* when LOW_SET = 1111, watchdog service is disabled

3.6.2.4

Central thermal sensor fault management

The central thermal sensor plays a major role in protecting the whole device. This sensor is monitoring the

temperature of the SPSB100 core. If SPSB100 core temperature exceeds the TSDC threshold a power-down is

run and SPSB100 reaches RECOVERY-2 state.

In RECOVERY-2 state all regulators are OFF, the TSD event counter TSD_CNT_FAIL is incremented. After the

temperature cooled down, if TSD_CNT_FAIL is less than 3 then SPSB100 transits to INIT state and initiates a

power-up sequence, if not then SPSB100 transits to DEEP-SLEEP state until a wake-up event and generates a

status register flag FORCED_SLEEP_TSD.

The TSD event counter, TSD_CNT_FAIL, is readable through SPI and can be cleared by CLR_TSD_CNT_FAIL

bit. This counter is incremented after a TSD event on any of the clusters.

SPSB100

Functional description

DS14640 - Rev 2

page 26/213

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