SPSB100 datasheet(17/213 Pages) STMICROELECTRONICS

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Figure 11. Behavior on battery over voltage

VFBB

# 0.15V

BOOST enable

IRQ

ACTIVE or REC-1 or REC-2 or INIT

state

VFBB_OV_EW

13.5V

IRQ flags :

EW = Early warning

VFBB_OV # 29V

VFBB_OV_EW programmable

from ~24V to 38V

executes

Power-Up

sequence

REC-1

Trig WD

ACTIVE

Safety

checks

REC-2  INIT

BYPASS enable

FBB overvoltage lockout



executes Power-Down sequence

40V

Always ON

(1)

(1) Digital comparator in ACTIVE – Full-Power & REC -1, programmable threshold.

Always OFF

3.3

BUCK converters

3.3.1

BUCK1 converter

The BUCK1 regulator is a synchronous converter compatible to battery level, with integrated power mos. Stability

compensation network is external.

Output voltages are programmable via USER-NVM through the bit BUCK1_PU_VALUE.

The switching frequency can be selected either at 400 kHz or 2.4 MHz, by USER-NVM BUCK1_FREQ. To limit

emission in audio bandwidth, refresh frequency can be forced at 25 kHz by USER-NVM bit

BUCK1_REFRESH_FREQ set low (1 kHz when high). The draw back will be an extra consumption in low power

mode.

The spread spectrum feature is configurable by SPI bit BUCK1_SPREAD_ENA (disabled by default).

BUCK1 integrates a low power mode (automatically set by LOW_POWER_SET by SPI) that optimizes its

efficiency in active low power mode. (BUCK1 is a mandatory regulator in active low power mode).

BUCK1 can be disabled by the SPI bit VBUCK1_ENA (only after SPI_PROTECT_ACCESS has been set). In

active low power mode, the action of enable BUCK1 is not allowed.

The live bit VBUCK1_ENA_STATUS reflects the state of BUCK1 output.

Note:

After first power up is needed to align the live bit associated in DSR18 (VBUCK1_ENA_STATUS) with the

current value associated in DCR1.

In active full power, the BUCK1 converter provides the following diagnostics:

•

UV detection to monitor the output voltage (flag is BUCK1_UV). BUCK1 is therefore switched off after

timing tbuck1_UV_TO except if SPI bit MASK_BUCK1_UV_POWER_OFF is set.

•

Undervoltage detection generates an IRQ except if MASK_BUCK1_IRQ is set.

•

OV detection to monitor the output voltage (flag is BUCK1_OV bit) BUCK1 is therefore switched off after

timing tbuck1_OV_TO. Status register bit BUCK1_OV must be read and cleared before switching ON the

regulator by SPI bit VBUCK1_ENA to allow a proper start-up (only when BUCK1 is not critical for MCU).

•

Overvoltage detection generates an IRQ except if MASK_BUCK1_IRQ is set.

SPSB100

Functional description

DS14640 - Rev 2

page 17/213

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