SPSB100 datasheet(27/213 Pages) STMICROELECTRONICS

27 / 213 page

Figure 16. State machine details onTSDC fault

ACTIVE

state

WD trigger OK*

LOW-POWER

mode

FULL-POWER

mode

SPI cmd

WD trigger OK*

TSD event & T ° cooled down & cnt < 3

Execute

Power-Up

sequence

Finished OK

DEEP-SLEEP

state

INIT

state

Wake-up

event

REC-1

state

TSDC

Execute

Power-Down

sequence

REC-2

state

TSD event & not T ° cooled down

TSD event & cnt ≥ 3

TSDC

NFSO asserted

VFBB_OK_R < VFBB < VFBB_OV

* when LOW_SET = 1111, watchdog service is disabled

(WD LOW trigger OK*) & (all flag cleared)

3.6.2.5

Regulator faults management

Each SPSB100 regulator has the following monitors:

•

Temperature sensor with a warning threshold (TW) and a shut-down threshold (TSD)

•

Undervoltage comparator (UV) except for LDO1

•

Overvoltage comparator (OV)

•

Power-good comparator (PG_TIMEOUT)

•

Overcurrent comparator (OC) on BUCKs

•

Internal regulator comparator (INT_FAIL) on BUCKs

•

FB pin disconnection (FBLOSS for BUCK1 and BUCK2)

The user can decide how SPSB100 shall react on an event of those monitors, this is done through the USER-

NVM bit REGFAIL_GO_REC of each of them.

A TW event sets the associated flag and generates an interruption, while the reaction to a TSD, UV,

PG_TIMEOUT, OC, INT_FAIL, FBLOSS and OV event depends on the regulator REGFAIL_GO_REC bit.

When REGFAIL_GO_REC is set to ‘1’, a fault detected on regulator TSD, UV, PG_TIMEOUT, OC, INT_FAIL,

FBLOSS and OV monitors will initiate a power-down sequence, then the state machine transits to INIT state and

runs a power-up sequence: if a fault is detected then the retry sequence described in the Section 3.6.2.3: Power-

up fault management is executed. In the case of TSD the SPSB100 reaction is the same as for the TSDC event

described in the Section 3.6.2.4: Central thermal sensor fault management.

A fault event counter REG_FAIL_CNT is incremented when a power-down sequence is initiated by a regulator

fault event. When the counter reaches 3, SPSB100 transits to DEEP-SLEEP state where the counter is reset and

the SPI flag FORCED_SLEEP_REGFAIL is set. REG_FAIL_CNT is cleared by SPI bit CLR_REG_FAIL_CNT.

SPSB100

Functional description

DS14640 - Rev 2

page 27/213

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