SPSB100 datasheet(25/213 Pages) STMICROELECTRONICS

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3.6.2.3

Power-up fault management

The power-up sequence can be programmed to wait the power-good signal of any of the turned-on regulator (see

the power-up sequence description in the Section 3.7.1: Power-up sequence for details). In such case a timeout

counter runs, it is longer than the maximum rising time of SPSB100 regulators.

If the timeout elapses, the SPSB100 executes a power-down sequence, the power-up retry counter

POWUP_RETRY_CNT is incremented and SPSB100 retries 4 times to power-up the regulators

(POWUP_RETRY_CNT counter can be cleared by CLR_POWUP_RETRY_COUNT bit). If 4 successive faults

occur and the PU_LOOP_FOR_EVER bit is not set, then SPSB100 enters in DEEP-SLEEP state, clears the

POWUP_RETRY_CNT and generates a status register flag FORCED_SLEEP_POWUP. If the

PU_LOOP_FOR_EVER bit is set SPSB100 retries to power-up forever.

The same retry loop applies if a fault on a regulator is detected during the power-up sequence and the regulator

has its REGFAIL_GO_REC configuration bit set to 1. See the Section 3.7.1: Power-up sequence for details.

Figure 14. State machine details on power-up fault (1)

DEEP-SLEEP

state

Wake-up

event

REC-1

state

Execute

Power-Up

sequence

Finished OK

INIT

state

Execute

Power-Down

sequence

(retry ≤ 3)

OR (for_ever = 1) ?

Retry loop

NFSO asserted

PG_TimeOut reached

OR REGfail & GoREC=1

VFBB_OK_R < VFBB < VFBB_OV

The behavior is similar if the power-up sequence timeout is reached when the sequence is executed after a

watchdog trig fault or a FCCU monitor fault detection as shown in the following figure.

SPSB100

Functional description

DS14640 - Rev 2

page 25/213

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