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SPSB100 Datenblatt(PDF) 12 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 12 Page - STMicroelectronics |
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12 / 213 page ![]() 3 Functional description 3.1 Supply configurations The battery supplies the boost controller. FBB, the boost output, supplies internal regulated voltages of analog and digital blocks, the wake-up blocks, OUT_HS output and fail-safe block. BUCK1, BUCK2 and BUCK3 have independent supply pins to allow different supply configurations according to the applications. Here we describe the two main configurations where it is required to provide direct or indirect supply to the microcontroller core. 3.1.1 System supply configuration 1 Figure 5. Configuration 1: direct supply of the microcontroller core SR6G7 BUCK1 BUCK3 LDO1 5 V 0.98V 3.3V SPI SPSB100B VIO SPI Communication BUCK2 5.0V LDO2 VDD_HV +VDD_HV_IO + VDD_HV_LP Battery 5.0V Ext. LP domain standby NVM CORE SPI VDD_LV BOOST I/O Ext. load VDD_HV_NVM ADC VDD_HV_ADR VDD_HV_ADV Filter In this configuration BUCK3 is supplied by BUCK1 and is configured to provide a 0.98 V high current supply to the micro core. BUCK1 and BUCK2 are supplied by the boost and supply respectively the 3.3 V and the 5 V rails with a switching frequency of 400 kHz. Boost supplies always LDO1 and LDO2, both providing 5 V for external loads. The power-up and power-down sequence associated to such supply configuration are the following: Power-up sequence 1. Turn ON BUCK1 at 3.3 V, wait PG (BUCK1_PG_OK flag); 2. Turn ON BUCK3 at 0.98 V, wait PG (BUCK3_PG_OK flag); 3. Turn ON BUCK2 at 5 V, wait PG (BUCK2_PG_OK flag); 4. Turn ON LDO2 in tracker of buck 2, wait PG (LDO2_PG_OK flag); 5. Turn ON LDO1, wait PG (LDO1_PG_OK flag). 6. Deassert NRST, wait 0 ms Power-down sequence 1. Assert NRST, wait 2 ms; 2. Turn OFF LDO2 and LDO1, wait 2 ms; 3. Turn OFF BUCK3, wait 2 ms; 4. Turn OFF BUCK1 and BUCK2, wait 2 ms; 5. Turn OFF VREG after 10 ms. SPSB100 Functional description DS14640 - Rev 2 page 12/213 |
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