SPSB100 datasheet(167/213 Pages) STMICROELECTRONICS

167 / 213 page

Bit

Name

Description

1: Indicates that an internal occurs on BUCK2

Bit is latched until a “read and clear” command

BUCK1_INT_FAIL

BUCK1 internal fail that may be caused by LDO_BUCK1_OV or LDO_BUCK1_UV

1: Indicates that an internal occurs on buck1

Bit is latched until a “read and clear” command

LBIST_ERROR_1

1: The logic BIST2 reported an error

LBIST_ERROR_0

1: The logic BIST1 reported an error

ABIST_ERROR

1: The analog BIST reported an error

Table 223. DSR3 (0x23)

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

0 (RC1L)

CURRENT_MISMATCH

FORCED_SLEEP_TSD

FCCUFAIL

WDFAIL

INT_REG_UV

INT_REG_OV

NVM_COMP_ERROR

NVM_CRC_ERROR

Current mismatch bit

Forced sleep after TSD event

bit

FCCU fail bit

Watchdog fail

bit

Interrupt regulator

undervoltage bit

Interrupt regulator

overvoltage bit

NVM compare error bit

NVM CRC error bit

Table 224. DSR3 (0x23) description

Bit

Name

Description

15 CURRENT_MISMATCH 1: A current mismatch occurs between main and monitoring currents

14 FORCED_SLEEP_TSD 1: state machine reaches DEEP-SLEEP after 3 TSD events

FCCUFAIL

FCCU fault detection

1: A fault has been detected by the FCCU monitor bit is latched until a "Read and clear"

command

WDFAIL

A WD trig fail event occurred

Bit is latched until a "Read and clear" command

Note that after 15 consecutive WD trig faults the device reach DEEP-SLEEP state where

WDFAIL_CNT is cleared, while WDFAIL bit is kept at 1

INT_REG_UV

Internal regulator undervoltage

1: Indicates an internal regulator under voltage occurs on 3V3

This bit is latched until a “read and clear” command

INT_REG_OV

Internal regulator overvoltage

1: Indicates an internal regulator over voltage occurs on 3V3

This bit is latched until a “read and clear” command

NVM_COMP_ERROR

Indicates an error between NVM and mirror register

NVM_CRC_ERROR

Indicates a NVM CRC error at NVM download

Table 225. DSR3 (0x33) LSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (RC1L)

GNDLOSS

OSC_ERROR

SPI_REG_COMP_ERROR

FSM_COMP_ERROR

CRC3

CRC2

CRC1

CRC0

Ground Loss

detection bit

Oscillators error

bit

SPI registers compare error

bit

Finite state machine

compares error bit

Cyclic

redundancy

checking bit 3

Cyclic

redundancy

checking bit 2

Cyclic

redundancy

checking bit 1

Cyclic

redundancy

checking bit 0

SPSB100

SPI registers

DS14640 - Rev 2

page 167/213

SPSB100 Datenblatt(PDF) 167 Page - STMicroelectronics

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