SPSB100 datasheet(119/213 Pages) STMICROELECTRONICS

119 / 213 page

9.5

Control registers

Table 59. DCR1 (0x01) MSB

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

- (R0)

0 (R/W)

RES

WD_TIME_3

WD_TIME_2

Reserved

Watchdog trigger time 3

Watchdog trigger time 2

Table 60. DCR1 (0x01) MSB description

Bit

Name

Description

RES

Reserved

RES

Reserved

RES

Reserved

RES

Reserved

RES

Reserved

RES

Reserved

17 WD_TIME_3

Watchdog trigger time

0000: Window 1

0001: Window 2 (default window once WD kick)

0010: Window 3

0011: Window 4

0100: Window 5

0101: Window 6

0110: Window 7

0111: Window 8

1000: Window 9

1001-1110: Window 10 → 5-50 ms window

1111: Stop watchdog

The modified WD trigger time is valid after the next WD trig (CSN transition low-high) protected by

SPI_PROTECT_ACCESS bit

16 WD_TIME_2

Table 61. DCR1 (0x01)

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

0 (R/W)

1 (R/W)

0 (R/W)

WD_TIME_1

WD_TIME_0

VBUCK3_ENA

VBUCK2_ENA

VBUCK1_ENA

LDO1_ENA

LDO2_ENA

LOW_POWER_SET

Watchdog

trigger time 1

Watchdog

trigger time 0

BUCK3 enable

bit

BUCK2 enable

bit

BUCK1 enable

bit

LDO1 enable

bit

LDO2 enable

bit

Set low power mode

Table 62. DCR1 (0x01) description

Bit

Name

Description

WD_TIME_1

WD_TIME_0

VBUCK3_ENA

BUCK3 enable bit (default value link to start up sequence setting)

SPSB100

SPI registers

DS14640 - Rev 2

page 119/213

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