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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SPSB100 Datenblatt(PDF) 120 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 120 Page - STMicroelectronics |
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120 / 213 page  Bit Name Description 1: Enable Protected by SPI_PROTECT_ACCESS bit 0: Disabled Note that, after the first power-up is needed to align the live bit associated in DSR18 (VBUCK3_ENA_STATUS) with the current value associated in DCR1 12 VBUCK2_ENA BUCK2 enable bit (default value link to start up sequence setting) 1: Enable Protected by SPI_PROTECT_ACCESS bit 0: Disabled Note that, after the first power-up is needed to align the live bit associated in DSR18 (VBUCK2_ENA_STATUS) with the current value associated in DCR1 11 VBUCK1_ENA BUCK1 enable bit (default value link to start up sequence setting) 1: Enable Protected by SPI_PROTECT_ACCESS bit 0: Disabled Note that, after the first power-up is needed to align the live bit associated in DSR18 (VBUCK1_ENA_STATUS) with the current value associated in DCR1 10 LDO1_ENA LDO1 enable bit (default value link to start up sequence setting) 1: Enable 0: Disabled Protected by SPI_PROTECT_ACCESS bit Note that, after the first power-up is needed to align the live bit associated in DSR18 (LDO1_ENA_STATUS) with the current value associated in DCR1 9 LDO2_ENA LDO2 enable bit (default value link to start up sequence setting) 1: Enable 0: Disabled Protected by SPI_PROTECT_ACCESS bit Note that, after the first power-up is needed to align the live bit associated in DSR18 (LDO2_ENA_STATUS) with the current value associated in DCR1 8 LOW_POWER_SET Set low power mode 1: Go to low power 0: Back to full power Protected by SPI_PROTECT_ACCESS bit Table 63. DCR1 (0x01) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) WD_LP_ENA DO_POWER_DOWN U- NVM_PROG DO_POWER_CYCLE CRC3 CRC2 CRC1 CRC0 Watchdog in low power mode enable bit Power-down sequence bit User NVM program bit Power cycle bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 64. DCR1 (0x01) LSB description Bit Name Description 7 WD_LP_ENA 1: Watchdog is enabled in low power mode (default) SPSB100 SPI registers DS14640 - Rev 2 page 120/213 |
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