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SPSB100 Datenblatt(PDF) 125 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 125 Page - STMicroelectronics |
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125 / 213 page ![]() Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Reserved BOOST monitor threshold bit 2 BOOST monitor threshold bit 1 BOOST monitor threshold bit 0 Software debug exit bit VS undervoltage early warning threshold bit 4 VS undervoltage early warning threshold bit 3 VS undervoltage early warning threshold bit 2 Table 78. DCR4 (0x04) MSB description Bit Name Description 23 RES Reserved 22 BOOST_DSMON_TH_2 Control BOOST_VDMON_TH 000: 0.3 V 001: 0.5 V 010: 0.7 V 011: 0.9 V 100: 1.1 V 101: 1.3 V 110: 1.5 V 111: 1.7 V 21 BOOST_DSMON_TH_1 20 BOOST_DSMON_TH_0 19 SWDBG_EXIT This bit is active in software debug mode 1: Forces the device to exit software debug mode Watchdog restarts with a LOW 0: No action (default) 18 VS_UV_EW_TH_4 VS undervoltage early warning threshold At VS < VS_EW_TH, an interrupt is generated on IRQ pin and the status bit VS_UV_EW in SR4 is set (in active mode) 00000: Feature deactivated (default) 00001: 2.5 V … (0.25 V step) 11111: 10 V 17 VS_UV_EW_TH_3 16 VS_UV_EW_TH_2 Table 79. DCR4 (0x04) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 1 (R/W) 0 (R/W) VS_UV_EW_TH_1 VS_UV_EW_TH_0 FCCU_PROTOCOL FCCU_STATIC_ERROR OUTHS_1 OUTHS_0 BYPASS_DSMON_TH_2 BYPASS_DSMON_TH_1 VS undervoltage early warning threshold bit 1 VS undervoltage early warning threshold bit 0 FCCU protocol bit FCCU static error bit OUTHS configuration bit 1 OUTHS configuration bit 0 BYPASS monitor threshold bit 2 BYPASS monitor threshold bit 1 Table 80. DCR4 (0x04) description Bit Name Description 15 VS_UV_EW_TH_1 14 VS_UV_EW_TH_0 13 FCCU_PROTOCOL 1: Toggle (pull-up/down defined by FCCU_STATIC_ERROR) 0: Static (error state defined by FCCU_STATIC_ERROR) SPSB100 SPI registers DS14640 - Rev 2 page 125/213 |
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