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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SPSB100 Datenblatt(PDF) 126 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 126 Page - STMicroelectronics |
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126 / 213 page  Bit Name Description 12 FCCU_STATIC_ERROR 1: Error when FIN1 = 1 (→ pull-up active) 0: Error when FIN1 = 0 (→ pull-down active) 11 OUTHS_1 OUTHS configuration bits 00: Off (default) 01: On 1x: Timer 1 10 OUTHS_0 9 BYPASS_DSMON_TH_2 8 BYPASS_DSMON_TH_1 Table 81. DCR4 (0x04) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) BYPASS_DSMON_TH_0 CLR_REG_FAIL_CNT KILL_SWDBG_TIMEOUT WD_TRIG CRC3 CRC2 CRC1 CRC0 BYPASS monitor threshold bit 0 Clear REG_FAIL_CNT bits Kill software debug timeout bit Watchdog trigger bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 82. DCR4 (0x04) LSB description Bit Name Description 7 BYPASS_DSMON_TH_0 6 CLR_REG_FAIL_CNT Clear REG_FAIL_CNT to 0 This bit is always read low 5 KILL_SWDBG_TIMEOUT Kill the 10s timeout that runs when the SWDBG pin is shorted to VIO at start-up. With this bit at '1' the timeout is killed → state machine exits from SWDBG state and transits to REC-1 and the watchdog is started with a LOW. SWDBG mode is then NOT entered. This feature allows the MCU to take control of SPSB100 in case of hardware fault without waiting the 10 s timeout to elapse. 4 WD_TRIG Watchdog trig alternatively with 0 and 1. First trig has to be with 1 Watchdog trig alternatively with 0 and 1 3 CRC 3 2 CRC 2 1 CRC 1 0 CRC 0 Table 83. DCR5 (0x05) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) RES CLR_REC2_FROM_DO_POWER_CYCLE CLR_DEEP_SLEEP_FROM_DO_POWER_DOWN CLR_POWUP_RETRY_COUNT T1_ENA_2 T1_ENA_1 T1_ENA_0 T1_PER_2 Reserved Clear REC2_FROM_DO_POWER_CYCLE bit Clear DEEP_SLEEP_FROM_DO_POWER_DOWN bit Clear POWUP_RETRY_COUNT bit Timer 1 enable bit 2 Timer 1 enable bit 1 Timer 1 enable bit 0 Timer 1 period bit 2 Table 84. DCR5 (0x05) MSB description Bit Name Description 23 RES Reserved 22 CLR_REC2_FROM_DO_POWER_CYCLE Clear REC2_FROM_DO_POWER_CYCLE to 0 SPSB100 SPI registers DS14640 - Rev 2 page 126/213 |
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