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SPSB100 Datenblatt(PDF) 136 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 136 Page - STMicroelectronics |
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136 / 213 page ![]() Bit Name Description 13 BUCK1_PD_STEP_OFF_2 12 BUCK1_PD_STEP_OFF_1 11 BUCK1_PD_STEP_OFF_0 To define BUCK1 turn-off steps 000: Step 1 001: Step 2 010: Step 3 011: Step 4 100: Step 5 101: Step 6 11X: Step 7 10 BUCK1_IPEAK_2 9 BUCK1_IPEAK_1 8 BUCK1_IPEAK_0 BUCK1 peak limitation current 000: 2.0 A 001: 2.5 A 010: 3.0 A 011: 3.5 A 100: 4.0 A 101: 4.5 A 11X: 5.0 A Table 111. DCR10 (0x0A) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - (R) - (R) - (R) - (R) - (R) - (R) - (R) - (R) BUCK1_REGFAIL_GO_REC BUCK1_SS_VALUE_1 BUCK1_SS_VALUE_0 BUCK1_REFRESH_FREQ CRC3 CRC2 CRC1 CRC0 BUCK1 regulator fail receive bit BUCK1 soft start value bit 1 BUCK1 soft start value bit 0 BUCK1 refresh frequency bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 112. DCR10 (0x0A) LSB description Bit Name Description 7 BUCK1_REGFAIL_GO_REC 1: A fail on BUCK1 regulator initiates a power-down sequence and moves the state machine to REC-2 state 0: A fail on BUCK1 regulator sends an IRQ (UV, OV, PG_nok, TW are maskable by SPI, but not TSD), and turns the regulator OFF if the fail is unmasked (UV, PG_nok are maskable by SPI, but not OV and TSD. TW never turns the regulator OFF) 6 BUCK1_SS_VALUE_1 5 BUCK1_SS_VALUE_0 BUCK1 soft start setting 00: 16.5 V/ms 01: 8.25 V/ms 10: 3.3 V/ms 11: 1.65 V/ms 4 BUCK1_REFRESH_FREQ 1: Refresh frequency 1 kHz 0: Refresh frequency 25 kHz 3 CRC3 2 CRC2 SPSB100 SPI registers DS14640 - Rev 2 page 136/213 |
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