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SPSB100 Datenblatt(PDF) 110 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 110 Page - STMicroelectronics |
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110 / 213 page ![]() 9 SPI registers 9.1 Global status byte GSB Table 51. Global status byte GSB Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 1 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) GSBN RSTB SPIE RES FE1 DE GW FS Global status bit inverted Reset SPI error Reserved Functional error bit 1 Device error Global warning Fail-safe Table 52. Global status byte GSB description Bit Name Description 31 GSBN Global status bit inverted The GSBN is a logically NOR combination of GSB bits 0 to bit 6(1). This bit can also be used as a global status flag without starting a complete communication frame as it is present at SDO directly after pulling CSN low. 0: Error detected (one or several GSB bits from 0 to 6 are set) 1: No error detected (default after power-on) Specific fault detection may be masked in the configuration registers 0x3F. A masked fault detection will still be reported in the GSB by the related fault flag, however it is not reflected in the GSBN (see the Section 5.2.2: Communication protocol for masks). 30 RSTB Reset The RSTB indicates that the NRESET output has been asserted low, this flag is set in case of: • Power-down sequence • WDFAIL (SR3 - 0x23) • FCCU fail (SR3 - 0x23) 0: No reset signal has been generated (default) 1: Reset signal has been generated RSTB is cleared by a read and Clear command to all bits in status register 1 causing the reset event. 29 SPIE SPI error bit The SPIE indicates errors related to a wrong SPI communication. • SPI_SDI_STUCK_HIGH (SR4 - 0x24) • SPI_SDI_STUCK_LOW (SR4 - 0x24) • SPI_CSN_TIMEOUT (SR4 - 0x24) • SPI_CRC_ERR (SR4 - 0x24) • SPI_UNDEF_ADD (SR4 - 0x24) • SPI_STATUS_WRT (SR4 - 0x24) • SPI_CLK_CNT (SR4 - 0x24) • SPI_LBISTED (SR4 - 0x24) 0: No error (default) 1: Error detected 28 RES Reserved 27 FE1 Functional error bit 1 The FE1 is a logical OR combination of errors coming from functional blocks. • OUTHS_OC (SR2 - 0x22) • OUTHS_OL (SR2 - 0x22) • BUCK1_UV (SR1 - 0x21) • BUCK2_UV (SR1 - 0x21) SPSB100 SPI registers DS14640 - Rev 2 page 110/213 |
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