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SPSB100 Datenblatt(PDF) 111 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 111 Page - STMicroelectronics |
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111 / 213 page ![]() Bit Name Description • BUCK3_UV (SR1 - 0x21) • BUCK1_OV (SR1 - 0x21) • BUCK2_OV (SR1 - 0x21) • BUCK3_OV (SR1 - 0x21) • BUCK1_OC (SR1 - 0x21) • BUCK2_OC (SR1 - 0x21) • BUCK3_OC (SR1 - 0x21) • LDO2_UV (SR1 - 0x21) • LDO2_OV (SR1 - 0x21) • BUCKX_PG_TIMEOUT from SPI request (SR1 - 0x21) • LDO2_PG_TIMEOUT from SPI request (SR1 - 0x21) 0: No error (default) 1: Error detected FE1 is cleared by a read and clear command to all related bits in status registers 3, 5 and 6 26 DE Device error bit DE is a logical OR combination of global errors related to the device. • FBB_OV (SR2 - 0x22) • FBB_UV (SR2 - 0x22) • VIO_UV (SR2 - 0x22) • TSD_CLx (SR2 - 0x22) • WD_ENA_ECHO_ERROR (SR2 - 0x22) • FCCU_ENA_ECHO_ERROR (SR2 - 0x22) • NFSO1_ECHO_ERROR (SR2 - 0x22) • IRQ_ECHO_ERROR (SR2 - 0x22) • NRST_ECHO_ERROR (SR2 - 0x22) 0: No error (default) 1: Error detected DE is cleared by a read and clear command to all related bits in status registers 2, 4 and 7 25 GW Global warning bit GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change or switch off of functions. • FBB_UV_EW (SR4 - 0x24) • FBB_OV_EW (SR4 - 0x24) • VS_UV_EW (SR4 - 0x24) • TW_CLx (SR4 - 0x24) 0: No error (default) 1: Error detected GW is cleared by a read and clear command to all related bits in status register 2 and 4 24 FS Fail-safe The FS bit indicates that the device was forced into DEEP-SLEEP, RECOVERY-1 or -2 state due to the following fault conditions: • FCCUFAIL (SR3 - 0x23) • WDFAIL (SR3 - 0x23) • FORCED_SLEEP_TSD (SR3 - 0x23) • FORCED_SLEEP_POWUP (SR5 - 0x25) • GNDLOSS (SR3 - 0x23) • INT_REG_UV (SR3 - 0x23) • INT_REG_OV (SR3 - 0x23) • CURRENT_MISMATCH (SR3 - 0x23) • OSC_ERROR (SR3 - 0x23) • ABIST_ERROR (SR3 - 0x23) • LBIST_ERROR (SR3 - 0x23) • NVM_COMP_ERROR (SR3 - 0x23) • NVM_CRC_ERROR (SR3 - 0x23) • SPI_REG_COMP_ERROR (SR3 - 0x23) SPSB100 SPI registers DS14640 - Rev 2 page 111/213 |
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