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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SPSB100 Datenblatt(PDF) 112 Page - STMicroelectronics |
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SPSB100 Datenblatt(HTML) 112 Page - STMicroelectronics |
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112 / 213 page  Bit Name Description • FSM_COMP_ERROR (SR3 - 0x23) All control registers are set to default Control registers are blocked for WRITE access except the following bits: • Error flags • Wake-up settings • Timer setting 1: Fail-safe active FS is cleared by a read and clear command to all related bits in status register SR3 and SR5 9.2 Control register overview Table 53. Control register overview (bit 31...28) upper nibbles Bit Mode 31 30 29 28 OpCode + address OC1 OC2 A5 A4 R/W Control register Bit Mode Addr 23 22 21 20 15 14 13 12 7 6 5 4 0x00 MSB Reserved Reserved LSB Reserved 0x01 DCR1 MSB RES RES RES RES R/W WD_TIME_1 WD_TIME_0 VBUCK3_ENA VBUCK2_ENA LSB WD_LP_ENA DO_POWER_DOWN U-NVM_PROG DO_POWER_CYCLE 0x02 DCR2 MSB RES RES NFSO_ASSERT_LOW LBIST R/W FCCU_COUNTER_10 FCCU_COUNTER_9 FCCU_COUNTER_8 FCCU_COUNTER_7 LSB FCCU_COUNTER_2 FCCU_COUNTER_1 FCCU_COUNTER_0 FCCU_ENA 0x03 DCR3 MSB RES RES BUCK3_SPREAD_ENA BUCK2_SPREAD_ENA R/W BUCK3_FTUNE_1 BUCK3_FTUNE_0 BOOST_OFF FBB_OV_EW_TH_3 LSB FBB_UV_EW_TH_2 FBB_UV_EW_TH_1 FBB_UV_EW_TH_0 SPI_PROTECT_ACCESS 0x04 DCR4 MSB RES BOOST_DSMON_TH_2 BOOST_DSMON_TH_1 BOOST_DSMON_TH_0 R/W VS_UV_EW_TH_1 VS_UV_EW_TH_0 FCCU_PROTOCOL FCCU_STATIC_ERROR LSB BYPASS_DSMON_TH_0 CLR_REG_FAIL_CNT KILL_SWDBG_TIMEOUT WD_TRIG 0x05 DCR5 MSB RES CLR_REC2_FROM_DO_POWER_CYCLE CLR_DEEP_SLEEP_FROM_DO_POWER_DOWN CLR_POWUP_RETRY_COUNT R/W T1_PER_1 T1_PER_0 TIMER_WAKE_ENA IGN_CONFIG LSB WU_ENA WU_PU WU_FILT TIMER_ENA 0x06 DCR6 MSB RES MASK_BUCK3_PG_TIMEOUT_IRQ MASK_BUCK3_OC_IRQ MASK_BUCK3_PG_IRQ R/W MASK_BUCK2_IRQ MASK_BUCK1_PG_TIMEOUT_IRQ MASK_BUCK1_OC_IRQ MASK_BUCK1_PG_IRQ LSB MASK_FBB_UV_EW_IRQ MASK_LDO2_PG_IRQ MASK_LDO2_PG_TIMEOUT_IRQ MASK_LDO2_IRQ 0x07 DCR7 MSB RES MASK_LDO1_PG_IRQ MASK_LDO1_PG_TIMEOUT_IRQ MASK_LDO1_IRQ R/W MASK_VS_EW_IRQ RES MASK_CL4_TW_IRQ MASK_CL3_TW_IRQ LSB MASK_SPI_ERROR_IRQ MASK_NFSO1_ECHO_ERROR_IRQ MASK_WD_ENA_ECHO_ERROR_IRQ MASK_FCCU_ENA_ECHO_ERROR_IRQ 0x08 DCR8 MSB RES MASK_SWDBG_VIO_IRQ MASK_LP_READY_IRQ CLR_TSD_CNT_FAIL R/W MASK_BUCK2_UV_POWER_OFF MASK_BUCK1_UV_POWER_OFF MASK_TW_GW MASK_OL_GSB LSB RES RES RES GO_INIT Table 54. Control register overview (bit 27...24) lower nibbles Bit Mode 27 26 25 24 OpCode + address A3 A2 A1 A0 R/W Control register Bit Mode Addr 19 18 17 16 11 10 9 8 SPSB100 SPI registers DS14640 - Rev 2 page 112/213 |
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