28HS01GTAM03 datasheet(25/138 Pages) INFINEON

25 / 138 page

Datasheet

25 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Address space maps

These are condensed tables that use a couple of sectors as references. There are address ranges that are not

explicitly listed. All 4KB sectors have the pattern xxxxx000h-xxxxxFFFh. All 256KB sectors have the pattern

xxx00000h-xxx3FFFFh, xxx40000h-xxx7FFFFh, xx80000h-xxxCFFFFh, or xxD0000h-xxxFFFFFh.

3.2

ID address space

This particular region of the memory is assigned to manufacturer, device, and unique identification:

• The manufacturer identification is assigned by JEDEC. (see Table 90)

• The device identification is assigned by Infineon®. (see Table 90)

• A 64-bit unique number is located in 8 bytes of the Unique Device ID address space. This Unique ID can be used

as a software readable serial number that is unique for each device. (see Table 91)

There is no address space defined for these IDs as they can be read by providing the respective transactions only.

The transactions do not need the address to read these IDs. The data in this address space is read-only data.

3.3

JEDEC JESD216 SFDP space

The SFDP standard provides a consistent method of describing the functional and feature capabilities of this

serial flash device in a standard set of internal parameter tables. These parameter tables can be interrogated by

host system software to enable adjustments needed to accommodate divergent features. The SFDP address

space has a header starting at address zero that identifies the SFDP data structure and provides a pointer to each

parameter. The SFDP address space is programmed by CYPRESS™ and read-only for the host system. (see

Table 86 through Table 89).

3.4

SSR address space

Each HS/L-T family memory device has a 1024-byte SSR which is OTP address space. This address space is

separate from the main flash array. The SSR area is divided into 32 individually lockable, 32-byte aligned and

length regions.

In the 32-byte region starting at address zero:

• The sixteen lowest bytes contain a 128-bit random number. The random number cannot be written to, erased

or programmed and any attempts will return an PRGERR flag.

• The next four bytes are used to provide one bit per secure region (32 bits in total) to permanently protect once

set to “0” from writing, erasing or programming.

• All other bytes are reserved.

The remaining regions are erased when shipped from CYPRESS™, and are available for programming of

additional permanent data.

Table 6

SFDP overview address map

Byte address

Description

0000h

Location zero within JEDEC JESD216D SFDP space - start of SFDP header

,,,

Remainder of SFDP header followed by undefined space

0100h

Start of SFDP parameter tables The SFDP parameter table data starting at 0100h

...

Remainder of SFDP parameter tables followed by either more parameters or undefined space

28HS01GTAM03 Datenblatt(PDF) 25 Page - Infineon Technologies AG

28HS01GTAM03 Datenblatt(HTML) 25 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL