28HS01GTAM03 datasheet(30/138 Pages) INFINEON

30 / 138 page

Datasheet

30 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.1.1.2

ECC status register (ECSV)

• An 8-bit ECC Status Register provides the status of 1-bit or 2-bit errors during normal reads since last ECC clear

or reset. ECC Status Register does not have user programmable nonvolatile bits, all defined bits are volatile read

only bits. The default state of these bits are set by hardware.

• ECC Status Register can be accessed through the Read Any Register transaction. The correct sequence for Read

Any Register based ECSV is read as follows:

- Read data from memory array using any of the Read transaction

- ECSV is updated by the device

- Read Any Register of ECSV provides the status of any ECC event since the last clear or reset.

• ECSV is cleared by POR, CS# Signaling Reset, Hardware/Software reset, or a Clear ECC Status Register trans-

action.

4.1.1.3

ECC error address trap (EATV)

• A 32-bit register is provided to capture the ECC data unit address where an ECC error is first encountered during

a read of the flash array. Only the address of the first enabled error type (“2-bit only” or “1-bit or 2-bit” as selected

in CFR4N[3]) encountered after POR, hardware reset, or the ECC Clear transaction is captured. The EATV Register

is only updated during Read transactions.

The EATV Register contains the address that was accessed when the error was detected. The failing bits may

not be located at the exact address indicated in the register, but will be located within the aligned 16-byte ECC

data unit where the error was detected. If errors are found in multiple ECC data units during a single read

operation, only the address of the first failing ECC unit address is captured in the EATV Register.

When 2-bit error detection is not enabled and the same ECC unit is programmed more than once, ECC error

detection for that ECC unit is disabled, therefore no error can be recognized to trap the address.

The Address Trap Register has a valid address when the ECC Status Register (ECSV) bit 3 or 4 = 1.

• The Address Trap Register can be read using the Read Any Register transaction.

• Clear ECC Status Register transaction, POR, or CS# Signaling/Hardware/Software reset clears the Address Trap

4.1.1.4

ECC error detection counter (ECTV)

• A 16-bit register is provided to count the number of 1-bit or 2-bit errors that occur as data is read from the flash

memory array. Only errors recognized in the main array will cause the Error Detection Counter to increment.

ECTV Register is only updated during Read transaction. Read ECC Status transaction does not affect the ECTV

The 16-bit Error Detection Counter will not increment beyond FFFFh. However, the ECC continues to work.

Note that during continuous read operations, when a 1-bit or a 2-bit error is detected, the clock may continue

toggling and the memory device will continue incrementing the data address and placing new data on the DQ

signals; any additional data units with errors that are encountered will be counted until CS# is brought back

HIGH.

During a read transaction only one error is counted for each data unit found with an error. Each read transac-

tion will cause a new read of the target data unit. If multiple read transactions access the same data unit

containing an error, the error counter will increment each time that data unit is read.

When 2-bit error detection is not enabled and the same data unit is programmed more than once, ECC error

detection for that data unit is disabled so, no error can be recognized or counted.

• The ECC Error Detection Counter Register can be read using the Read Any Register transaction.

• ECTV Register is set to 0 on POR, CS# Signaling/Hardware/Software Reset or with Clear ECC Status Register

transaction.

28HS01GTAM03 Datenblatt(PDF) 30 Page - Infineon Technologies AG

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