28HS01GTAM03 datasheet(56/138 Pages) INFINEON

56 / 138 page

Datasheet

56 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.8.2.3

Read Octal SDR transaction

The Read Octal SDR transaction provides high data throughput using SDR (8S-8S-8S) protocol. This protocol

supports the DS for capture of data. The option of wrapped read length is available. This transaction uses latency

cycles set by (CFR2V[3:0]) to enable maximum 166 or 200MHz clock frequency (see Transaction table on page

95).

4.8.2.4

Read Octal DDR transaction

The Read Octal DDR transaction provides the fastest data throughput using DDR (8D-8D-8D) protocol. This

protocol only supports the DS for capture of data. The option of wrapped read length is available. This transaction

uses latency cycles set by (CFR2V[3:0]) to enable maximum 166 or 200MHz clock frequency (see Transaction

table on page 95).

4.8.2.5

Read memory array related registers and transactions

4.8.3

Read registers transactions

There are multiple registers for reporting embedded operation status or controlling device configuration

options. Registers contain both volatile and nonvolatile bits. There are two ways to read the Registers. The Read

Any Register transaction provides a way to read all device registers: nonvolatile and volatile by address selection.

There are also dedicated Register Read transactions, which are defined per register and only read the contents

of that register. These Read Register Transactions support all three Protocols (1S-1S-1S), (8S-8S-8S) and

(8D-8D-8D) (see Transaction table on page 95).

4.8.3.1

Read any register

The Read Any Register transaction is the best way to read all device registers, both nonvolatile and volatile. The

transaction includes the address of the register to be read (see Transaction table on page 95). This is followed

by a number of latency cycles set by (CFR2V[3:0]) for reading nonvolatile registers and CFR3V[7:6] for reading

volatile registers. See Table 49 for NV Registers latency cycles and Table 51 for Volatile Registers latency cycles.

Then, the selected register contents are returned. In SPI mode, if the read access is continued, the same

addressed register contents are returned until the transaction is terminated; only one byte register location is

read by each Read Any Register transaction. For registers with more that one byte of data, the Read Any Register

transaction must again be used to read each byte of data. The Octal mode supports the DS for capture of data

(see Transaction table on page 95).

The maximum clock frequency for the Read Any Register transaction is 166MHz under SPI mode, 166MHz under

HL-T Octal mode, and 200MHz under HS-T Octal mode.

The Read Any Register transaction can be used during embedded operations to read Status Register 1 (STR1V).

It is not used for reading registers such as ASP PPB Access Register (PPAV) and ASP Dynamic Block Access Register

(DYAV). There are separate commands required to select and read the location in the array accessed. The Read

Any Register transaction will read invalid data from the PASS Register locations if the ASP Password protection

mode is selected by programming ASPR[2:0]. Reading undefined locations provides undefined data.

Table 30

Read memory array related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Configuration Register 2 (CFR2N, CFR2V)

(see

Table 48 on page 80)

Read (RDAY1_4_0, RDAY1_C_0)

Read Octal SDR (RDAY1_4_0)

Configuration Register 4 (CFR4N, CFR4V)

(see

Table 52 on page 83)

Read Fast (RDAY2_C_0)

Read Octal DDR (RDAY2_4_0)

Configuration Register 5 (CFR5N, CFR5V)

(see

Table 54 on page 85)

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