28HS01GTAM03 datasheet(97/138 Pages) INFINEON

97 / 138 page

Advanced

sector

protection

RDDYB_4_0

Read Dynamic Protection Bit transaction

reads the contents of the DYB Access

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 12

166

WRDYB_4_1

Write Dynamic Protection Bit transaction

writes to the DYB Access Register.

WRENB_0_0

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Input

Data

[7:0]

Figure 9

RDPPB_4_0

Read Persistent Protection Bit transaction

reads the contents of the PPB Access

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 12

PRPPB_4_0

Program Persistent Protection Bit

transaction programs / writes the PPB

WRENB_0_0

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 7

ERPPB_0_0

Erase Persistent Protection Bit

transaction sets all persistent protection

bits to 1.

WRENB_0_0

(CMD)

Figure 6

N/A

WRPLB_0_0

Write PPB Protection Lock Bit transaction

clears the PPB Lock to 0.

WRENB_0_0

(CMD)

RDPLB_0_0

Read Password Protection Mode Lock Bit

transaction shifts out the 8-bit PPB Lock

(CMD)

Figure 11

PWDUL_0_1

Password Unlock transaction sends the

64-bit password to flash device. If the

supplied password does not match the

hidden password in the Password Register,

the device is locked and only a hardware

reset or POR will return the device to

standby state, ready for new transactions

such as a retry of the PWDUL_0_1. If the

password does match, the PPB Lock bit is

set to 1.

(CMD)

Passwor

d [7:0]

Passwo

rd [15:8]

Passwo

[23:16]

Passwo

[31:24]

Passwo

[39:32]

Passwo

[47:40]

Passwor

d [55:48]

Passwor

d [63:56]

Figure 10

Reset

SRSTE_0_0

Software Reset Enable command is

required immediately before a SFRST_0_0

transaction.

(CMD)

Figure 6

N/A

SFRST_0_0

Software Reset transaction restores the

device to its initial power up state, by

reloading volatile registers from nonvolatile

default values.

SRSTE_0_0

(CMD)

Deep power

down

ENDPD_0_0

Enter Deep Power Down Mode transaction

shifts device in the lowest power

consumption mode.

(CMD)

Table 75

SPI (1S-1S-1S) transaction table (Continued)

Function

Transaction

name

Description

Prerequisite

transaction

Byte 1

(Hex)

Byte 2

(Hex)

Byte 3

(Hex)

Byte 4

(Hex)

Byte 5

(Hex)

Byte 6

(Hex)

Byte 7

(Hex)

Byte 8

(Hex)

Byte 9

(Hex)

Transaction

format

Max

frequency

(MHz)

Address

length

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