28HS01GTAM03 datasheet(76/138 Pages) INFINEON

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Datasheet

76 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Registers

5.1

5.2

Status register 1 (STR1x)

Status Register 1 contains both status and control bits. The functionality of supported Status Register 1 type is

described in Table 41.

Table 40

Bit Number

Name Function

Read/Write

Factory

Default

(binary)

Description

REGNAME#T[x]

T = N, V, O

Descending

Order

Possible Options:

N/A - Not Applicable

R - Readable Only

R/W - Readable and Writable

R/1 - Readable and OTP

Possible

Options:

Format:

Description of the Configuration bit

0 = Option ‘0’ selection of the Bit

1 = Option '1' selection of the Bit

Dependency: Is this Bit part of a function which

requires multiple bits for implementation?

Table 41

Status register 1[22]

Bit

number

Name

Function

Read/Write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

STR1N[7]

STR1V[7]

RESRVD

Reserved for Future

Use

N->R

V->R

This bit is Reserved for future use. This bit must always be

written/loaded to its default state.

STR1V[6]

PRGERR

Programming Error

Status Flag

V -> R

Description: The PRGERR bit indicates program operation success

or failure. When the PRGERR bit is set to a ‘1’, it indicates that there

was an error in the last programming operation. PRGERR bit is also

set when a program operation is attempted within a protected

memory region. When PRGERR is set, it can only be cleared with the

Clear Program and Erase Failure Flags (CLPEF_0_0) transaction or a

hardware/software reset.

Note The device will only go to standby mode once the PRGERR flag

is cleared.

Selection Options:

0 = Last programming operation was successful

1 = Last programming operation was unsuccessful

Dependency: N/A

STR1V[5]

ERSERR

Erasing Error Status

Flag

V -> R

Description: The ERSERR bit indicates erase operation success or

failure. When the ERSERR bit is set to a ‘1’, it indicates that there was

an error in the last erasing operation. ERSERR bit is also set when a

erase operation is attempted within a protected memory sector.

When ERSERR is set, it can only be cleared with the Clear Program

and Erase Failure Flags (CLPEF_0_0) transaction or a

hardware/software reset.

Note The device will only go to standby mode once the ERSERR flag

is cleared.

Selection Options:

0 = Last erase operation was successful

1 = Last erase operation was unsuccessful

Dependency: N/A

STR1N[4:2]

STR1V[4:2] LBPROT[2:0]

Legacy Block

Protection based

Memory Array size

selection

If PLPROT = 0

N -> R/W

V -> R/W

If PLPROT = 1

N -> R

V -> R

000

Description: The LBPROT[2:0] bits define the memory array size to

be protected against program and erase transactions. Based on the

LBPROT[2:0] configuration, either top 1/64, 1/4, 1/2, etc. or bottom

1/64, 1/4, 1/2, etc., or up to the entire array is protected.

Note If PLPROT bit - Permanent Locking selection of Legacy Block

Protection and 4KB Sector Architecture (CFR1x[4]) is set to a ‘1’, the

LBPROT[2:0] bits cannot be erased or programmed.

Selection Options:

000 = Protection is disabled

001 = 1/64th of the (top/bottom) array protection is enabled

010 = 1/32nd of the (top/bottom) array protection is enabled

…..

111 = All sectors are protected

Dependency: TBPROT (CFR1x[5])

Note

22. STR1x value during POR, Hardware Reset, Software Reset, DPD Exit, and CS# Signaling Reset is not valid.

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