28HS01GTAM03 datasheet(69/138 Pages) INFINEON

69 / 138 page

Datasheet

69 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

After the fourth CS# pulse, the slave triggers its internal reset, the device terminates any operation in progress,

makes all outputs high impedance, and ignores all read/write transactions for the duration of tRESET. Then the

device will be in standby state.

This reset sequence is not intended to be used at normal power on, but to be used only when the device is not

responding to the system. This reset sequence will be operational from any state that the device may be in.

Hence, CS# signaling reset is useful for packages that don't support a RESET# pin to provide behavior identical

to Hardware Reset.

Figure 60

CS# signaling reset protocol

4.13.4

Software reset

Software controlled Reset transaction restores the device to its initial power up state, by reloading volatile

registers from nonvolatile default values except the protection registers. It also terminates the embedded opera-

tions. A reset transaction (SFRST_0_0) is executed when CS# is brought HIGH at the end of the transaction and

requires tSR time to execute. See Table 85 for timing specifications.

The Reset Enable (SRSTE_0_0) transaction is required immediately before a Reset transaction (SFRST_0_0) such

that a software reset is a sequence of the two transactions. Any transaction other than SFRST_0_0 following the

SRSTE_0_0 transaction will clear the reset enable condition and prevent a later SFRST_0_0 transaction from

being recognized.

The Reset (SFRST_0_0) transaction immediately following a SRSTE_0_0 transaction, initiates the software reset

process. During software reset, only RDSR1_4_0, RDARG_C_0, and RDARG_4_0 of Status Register 1 are supported

operations as long as the volatile and nonvolatile configuration states of the device are the same. If the configu-

ration state is changing during software reset, reading Status Register 1 should only be done after the software

reset time has elapsed.

The software reset is independent of the state of RESET#. If RESET# is HIGH or Unconnected, and the software

reset transactions are issued, the device will perform software reset.

4.13.4.1

Software reset related registers and transactions

Table 37

Software reset related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

N/A

Software Reset Enable (SRSTE_0_0)

Software Reset (SFRST_0_0)

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