28HS01GTAM03 datasheet(91/138 Pages) INFINEON

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Datasheet

91 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Registers

5.22

INT# pin configuration register (INCV) - octal only

The INT# pin Configuration Register (INCV) configures which internal event will trigger a HIGH to LOW transition

on the INT# output pin.

Notes

• When INCV disables a particular feature from driving the INT# pin, it will prevent the corresponding INSV bit(s)

from being updated.

• Clearing a bit within INCV has no effect on INSV, and it is a system responsibility to independently clear the INSV

as required.

SECV[22:0]

SECVAL[22:0] Sector Erase Count

Value

V -> R

0x000000

Description: The SECVAL[22:0] bits store the number of

times a sector has been erased

Selection Options: Value

Dependency: N/A

Table 68

Interrupt configuration register

Bit

number

Name

Function

Read/Write

N = Nonvolatile

V = Volatile

Factory default

(binary)

Description

INCV[7]

INTBEN

INT# pin Enable

Selection

V -> R/W

Description: The INT# pin is an open-drain output used to

indicate to the host system that an event has occurred within

the memory device. The INTBEN bit enables or disables the

functionality controlling INT# pin.

Selection Options:

0 = INT# pin functionality is enabled

1 = INT# pin functionality is disabled

Dependency: N/A

INCV[6:5]

RESRVD

Reserved for Future

Use

V -> R/W

These bits are Reserved for future use. This bit must always be

written/loaded to its default state.

INCV[4]

REYBSY

Ready/Busy

Transition Selection

V -> R/W

Description: The REYBSY bit enables or disables whether

device ready/busy state will transition INT#.

Selection Options:

0 = A Busy to Ready transition will cause a HIGH to LOW

transition on the INT# output

1 = Ready/Busy transitions will not transition the INT# output

Dependency: N/A

INCV[3:2]

RESRVD

Reserved for Future

Use

V -> R/W

These bits are Reserved for future use. This bit must always be

written/loaded to its default state.

INCV[1]

ECC2BT

ECC 2-bit Error

Detection Selection0

V -> R/W

Description: The ECC2BT bit enables or disables whether a

2-bit ECC detection error will transition INT#.

Selection Options:

0 = 2-bit ECC detection will cause a HIGH to LOW transition the

INT# output

1 = 2-bit ECC detection will not transition the INT# output

Dependency: N/A

INCV[0]

ECC1BT

ECC 1-bit Error

Detection and

Correction Selection

V -> R/W

Description: The ECC1BT bit enables or disables whether a

1-bit ECC detection and correction error will transition INT#.

Selection Options:

0 = 1-bit ECC detection and correction will cause a HIGH to

LOW transition the INT# output

1 = 1-bit ECC detection and correction will not transition the

INT# output

Dependency: N/A

Table 67

Sector erase count register (Continued)

Bit

number

Name

Function

Read/Write

N = Nonvolatile

V = Volatile

Factory default

(binary)

Description

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