28HS01GTAM03 datasheet(8/138 Pages) INFINEON

8 / 138 page

Datasheet

8 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Interface overview

2.1

General description

The CYPRESS™ SEMPER™ Flash Octal family of products are high-speed CMOS, MIRRORBIT™NOR Flash devices

that are compliant with the JEDEC JESD251 eXpanded SPI (xSPI) specification. SEMPER™ is designed for

Functional Safety with development according to ISO 26262 standard to achieve ASIL-B compliance and ASIL-D

readiness.

SEMPER™ Flash with Octal Interface devices support both the Octal Peripheral Interface (OPI) as well as Legacy

x1 Serial Peripheral Interface (SPI). Both interfaces serially transfer transactions reducing the number of interface

connection signals. SPI supports SDR whereas OPI supports both SDR and DDR.

Read operations from the device are burst oriented. Read transactions can be configured to use either a wrapped

or linear burst. Wrapped bursts read from a single page whereas linear bursts can read the whole memory array.

The erased state of each memory bit is a logic 1. Programming changes a logic 1 (HIGH) to a logic 0 (LOW). Only

an erase operation can change a memory bit from a 0 to a 1. An erase operation must be performed on a complete

sector (4KBs or 256KBs).

SEMPER™ Flash provides a flexible sector architecture. The address space can be configured as either a uniform

256KB sector array, or a hybrid configuration 1 where thirty-two 4KB sectors are either grouped at the top or at

the bottom while the remaining sectors are all 256KB, or a hybrid configuration 2 where the thirty-two 4KB

sectors are equally split between the top and the bottom while the remaining sectors are all 256KB.

The Page Programming Buffer used during a single programming operation is configurable to either 256 bytes or

512 bytes. The 512 byte option provides the highest programming throughput.

Figure 2

Logic block diagram

Input/

Output

Drivers

Interface

CRC

Embedded

Microcontroller

Control Logic

(HIC/EAC)

Program Buffer

Read Buffer

ECC

(SECDED)

Data Integrity

Check

DS Generation

Clock

Reset Control

EnduraFlex

MirrorBit

Memory Array

Registers

Secure Silicon Region

SFDP and IDs

Address Register

CS#

SI / DQ0

RESET#

DQ2

SO / DQ1

DQ4

DQ3

DQ6

DQ5

DQ7

INT#

Power Management

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