28HS01GTAM03 datasheet(60/138 Pages) INFINEON

60 / 138 page

Datasheet

60 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.9.6

Write PPB lock bit

The Write PPB Lock Bit (WRPLB_0_0) transaction clears the PPB Lock Register PPLV[0] to zero. The PPBLCK bit is

used to protect the PPB bits. When PPLV[0] = 0, the PPB Program/Erase transaction will be aborted. In Read

Password Protection mode, PPBLCK bit is also used to control the high order bits of the address by forcing the

address range to be limited to one sector where boot code is stored, until the read password is supplied (see

Transaction table on page 95).

Before the WRPLB_0_0 transaction can be accepted by the device, a Write Enable (WRENB_0_0) transaction must

be issued and decoded by the device, which sets the Write/Program Enable (WRPGEN) in the Status Register 1 to

enable any write operations.

While the operation is in progress, the Status Register can still be read to check the value of the RDYBSY bit. The

WRPGEN bit is a 1 during the self-timed operation, and is a 0 when it is completed. When the Write PPB Lock

transaction is completed, the RDYBSY bit is set to a 0 (see Transaction table on page 95).

4.9.7

Write transactions related registers and transactions

4.10

Program

There are program transactions for programming data to the Memory Array, Secure Silicon Region and Persistent

Protection Bits.

These program transactions can use any of these three protocols:

• SPI interface with SDR (1S-1S-1S) protocol, transfers the one byte command one bit per CK rising edge

• Octal input interface with SDR (1S-1S-8S) and (1S-8S-8S) protocols, transfers the one byte command one bit

per CK rising edge (HL256T and HS256T Only)

• Octal interface with SDR (8S-8S-8S) protocol, transfers the two byte command eight bits per CK rising edge

• Octalinterface with DDR(8D-8D-8D) protocol,transfersthe two byte command eight bits per CK rising and falling

edge

Before any program transaction can be accepted by the device, a Write Enable (WRENB_0_0) transaction must

be issued and decoded by the device. Program transactions can only be executed by the device if the

Write/Program Enable (WRPGEN) in the Status Register is set to ‘1’ to enable program operations. When a

program transaction is completed, the WRPGEN bit is reset to a ‘0’.

While the program transaction is in progress, the Status Register 1 may be read to check the value of the Device

Ready/Busy (RDYBSY) bit. The RDYBSY bit is a ‘1’ during the self-timed program transaction, and is a ‘0’ when it is

completed.

The PGMERR bit in STR1V[6] may be checked to determine if any error occurred during the program transaction.

A program transaction applied to a sector that has been Write Protected through any of the protection schemes

will not be executed and will set the PGMERR status fail bit.

The program transactions will be initiated when CS# is driven into the logic HIGH state.

Table 32

Write transactions related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Status Register 1 (STR1N, STR1V)

(see Table 41 on page 76)

Write Enable (WRENB_0_0)

Configuration Register 5 (CFR5N, CRF5V)

(see Table 54 on page 85)

Write Disable (WRDIS_0_0)

ECC Status Register (ECSV)

(see Table 58 on page 86)

Clear Program and Erase Failure Flags

(CLPEF_0_0)

Clear Program and Erase Failure Flags

(CLPEF_0_0)

Interrupt Configuration (INCV)

(see Table 68 on page 91)

Clear ECC Status Register (CLECC_0_0)

Address Trap Register (EATV)

(see Table 59 on page 87)

Write Any Register (WRARG_C_1)

Write Any Register (WRARG_4_1)

ECC Detection Counter (ECTV)

(see Table 60 on page 87)

Write PPB Lock Bit (WRPLB_0_0)

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