28HS01GTAM03 datasheet(12/138 Pages) INFINEON

12 / 138 page

Datasheet

12 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Interface overview

•Examples:

- 1S-1S-1S means that the command is 1 bit wide SDR, the address is 1 bit wide SDR, and the data is one bit

wide SDR.

- 8D-8D-8D means that the command, address, and data transfers are always 8 bits wide DDR.

Protocols definition

• Protocol modes defined for the SEMPER™ Flash Octal Interface:

1.1S-1S-1S: One DQ signal used during command transfer, address transfer, and data transfer. All phases are

SDR.

2.8S-8S-8S: Eight DQ signals used during command transfer, address transfer, and data transfer. All phases are

SDR.

3.8D-8D-8D: Eight DQ signals used during command transfer, address transfer, and data transfer. All phases are

DDR.

1S-1S-1S protocol

• The 1S-1S-1S mode is the preferred default protocol following Power-On-Reset (POR), but flash devices can be

configured to reset into the Octal mode.

• Each transaction begins with an 8-bit (1-byte) command. The command selects the type of information transfer

or device operation to be performed.

• This protocol uses SI/DQ[0] to transfer information from host to flash device and SO/DQ[1] to transfer infor-

mation from flash device to host. On each DQ, information is placed on the DQ line in Most Significant bit (MSb)

to Least Significant bit (LSb) order within each byte. Sequential address bytes are transferred in highest order

to lowest order sequence. Sequential data bytes are transferred in lowest address to highest address order.

• In 1S-1S-1S, DQ[7:2] are not used for data transfer period. Hence, the DQ[7:2] signals will be high impedance.

1S-1S-8S protocol (HL256T / HS256T Only)

• Each transaction begins with an 8-bit (1-byte) command. The command selects the type of information transfer

or device operation to be performed.

n This protocol uses DQ[7:0] signals. The 8-bit command and address placed on the DQ[0] in MSb to LSb order.

Sequential data bytes in SDR are transferred in lowest address to highest address order on DQ[7:0].

1S-8S-8S protocol (HL256T / HS256T Only)

• Each transaction begins with an 8-bit (1-byte) command. The command selects the type of information transfer

or device operation to be performed.

n This protocol uses DQ[7:0] signals. The 8-bit command is placed on the DQ[0] in MSb to LSb order. The LSb of

address byte is placed on DQ[0] with each higher order bit on the successively higher numbered DQ signals.

Sequential address bytes are transferred in highest order to lowest order sequence. Sequential data bytes in

SDR are transferred in lowest address to highest address order on DQ[7:0].

8S-8S-8S and 8D-8D-8D protocols

• Each transaction begins with a 16-bit (two same bytes) command. The command selects the type of information

transfer or device operation to be performed.

• Supports 4-byte addressing only.

• This protocol uses DQ[7:0] signals. The LSb of each byte is placed on DQ[0] with each higher order bit on the

successively higher numbered DQ signals. Sequential address bytes are transferred in highest order to lowest

order sequence. Sequential data bytes in SDR are transferred in lowest address to highest address order.

Sequential data bytes in DDR are transferred only in byte pairs (words) where the byte order depends on the

order in which the bytes are written or programmed in that protocol mode. Sequential data bytes are transferred

in lowest address to highest address order.

28HS01GTAM03 Datenblatt(PDF) 12 Page - Infineon Technologies AG

28HS01GTAM03 Datenblatt(HTML) 12 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL