28HS01GTAM03 datasheet(31/138 Pages) INFINEON

31 / 138 page

Datasheet

31 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.1.1.5

INT# output

• HL-T/HS-T supports INT# output pin to indicate to the host system that an event has occurred within the flash

device. The user can configure the INT# output pin to transition to the active (LOW) state when:

- 2-bit ECC error is detected

- 1-bit ECC error is detected

- Transitioning from the Busy to the Ready state

The INT# pin is only available in BGA package. Operation is controlled with the Interrupt Configuration Register

(INCV) where the INT# output (normally HIGH) is enabled. The Interrupt Configuration Register determines

when an internal event is enabled to trigger a HIGH to LOW transition on the INT# output pin.

The Interrupt Status Register (INSV) indicates the enabled internal event(s) that have occurred since the last

time the INSV was cleared.

If enabled, the INT# output pin will then transition from HIGH to LOW upon the occurrence of an enabled event.

Once the host recognizes that INT# has transitioned to the LOW state the INSV Register can be read to deter-

mine which internal event was responsible. INT# output status during POR, Hardware Reset, Software Reset,

DPD Exit, or CS# Signaling Reset is not valid.

• The INCV and INSV can be accessed through Read Any Register transaction from the SPI and Octal interfaces.

Write Any Register transaction to INCV is only supported in the Octal interface.

• The INT# output can be forced to transition back to the HIGH state (returned HIGH by an external pull-up resis-

tance) using the following methods:

- Disable the INT# output by loading a 1 into bit 7 of the Interrupt Configuration Register.

- Reset the appropriate bit (by writing a 1) in the INSV bit that indicates which internal event occurred to cause

the output to go LOW. All INSV bits that are LOW and are also enabled in the INSV must be reset before the

INT# output will return HIGH.

- TheINT#outputwillalsobereturnedtothedefault(disabled,High-Z)statewithCS#SignalingReset,Hardware

Reset (RESET# = LOW) or a POR. Hardware Reset and POR disable all interrupts by setting the Interrupt Con-

figuration Register back to the default (all interrupts disabled) state.

- Clearing ECC Status Register after the ECC event forces the INT# output to HIGH state.

4.1.2

ECC related registers and transactions

Table 10

ECC related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Configuration Register - 4 (CFR4N, CFR4V)

(see Table 52 on page 83)

Read Any Register (RDARG_C_0)

Read Any Register (RDARG_4_0)

ECC Status Register (ECSV) (see Table 58 on page 86)

Write Enable (WRENB_0_0)

ECC Address Trap Register (EATV) (see Table 59 on page 87)

Write Any Register (WRARG_C_1)

Write Any Register (WRARG_4_1)

ECC Error Detection Counter Register (ECTV)

(see Table 60 on page 87)

Read ECC Status (RDECC_4_0)

Interrupt Configuration Register (INCV) (see Table 68 on page 91)

Clear ECC Status Register

(CLECC_0_0)

Clear ECC Status Register (CLECC_0_0)

Interrupt Status Register (INSV) (see Table 69 on page 92)-

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