28HS01GTAM03 datasheet(61/138 Pages) INFINEON

61 / 138 page

Datasheet

61 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.10.1

Program granularity

The HS/L-T family supports multi-pass programming (bit walking) where programming a “0” over a “1” without

performing the sector erase operation. Bit-walking is allowed for the non-AEC-Q100 industrial temperature range

(40°C to +85°C) of this device. It is required to perform only one programming operation (single-pass

programming) on each ECC data unit between erase operations for the higher temperature range (40°C to

+105°C) and (40°C to +125°C) devices and all AEC-Q100 devices.

Multi-pass programming without an erase operation will disable the device’s ECC functionality for that data unit.

Note that if 2-bit ECC is enabled, multi-pass Programming within the same sector will result in a Program Error.

4.10.2

Page programming

Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming

command to move data from the buffer to the memory array. This sets an upper limit on the amount of data that

can be programmed with a single programming transaction. Page Programming allows up to a page size (either

256- or 512-bytes) to be programmed in one operation. The page size is determined by the Configuration Register

3 bit CFR3V[4]. The page is aligned on the page size address boundary. It is possible to program from one bit up

to a page size in each Page Programming operation. It is recommended that a multiple of 16-byte length and

aligned Program Blocks be written. This ensures that ECC is not disabled. For the very best Page Program

throughput, programming should be done in full pages of 512 bytes aligned on 512-byte boundaries with each

Page being programmed only once.

4.10.3

Program page transaction

The Program Page transaction (PRPGE_4_1) programs data into the memory array. If data more than a page size

(256B or 512B) is sent to the device, then the space between the starting address and the page aligned end

boundary, the data loading sequence will wrap from the last byte in the page to the zero byte location of the same

page and begin overwriting any data previously loaded in the page. If less than a page of data is sent to the device,

then the sent data bytes will be programmed in sequence, starting at the provided address within the page,

without having any effect on the other bytes of the same page. The programming process is managed by the

device internal control logic. The PRGERR bit indicates if an error has occurred in the programming transaction

that prevents successful completion of programming. This includes attempted programming of a protected area

(see Transaction table on page 95).

Under Octal SDR mode, this transaction can be used for single byte command and its address can start at an

even or odd address. Under DDR mode, this command can only be used for programming multiples of 2-bytes

and the address must start at an even address.

4.10.4

Program secure silicon region transaction

The Program Secure Silicon transaction (PRSSR_4_1) programs data in the SSR, which is in a different address

space from the main array data and is OTP. The SSR is 1024 bytes, so the address bits from A31 to A10 must be

zero for this transaction (see Transaction table on page 95). It is required to align start address to 32 bits while

programming the SSR space, which means the address bits A1 and A0 should be 0'b and host should deassert CS#

to align with 32 bits.

The PRGERR bit in STR1V[6] may be checked to determine if any error occurred during the operation.

To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to 1.

Each SSR memory space can be programmed one or more times, provided that the region is not locked.

Attempting to program zeros in a region that is locked will fail with the PRGERR bit in STR1V[6] set to 1.

Programming once, even in a protected area does not cause an error and does not set PRGERR bit. Subsequent

programming can be performed only on the unprogrammed bits (that is, 1 data). Programming more than once

within an ECC unit will disable ECC on that data unit.

28HS01GTAM03 Datenblatt(PDF) 61 Page - Infineon Technologies AG

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