28HS01GTAM03 datasheet(59/138 Pages) INFINEON

59 / 138 page

Datasheet

59 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.9.3

Clear program and erase failure flags transaction

The Clear Program and Erase Failure Flags (CLPEF_0_0) transaction resets bit STR1V[5] (Erase Error Flag) and bit

STR1V[6] (Program Error Flag) to 0. This transaction will be accepted even when the device remains busy with

RDYBSY set to 1, as the device does remain busy when either error bit is set. The WRPGEN bit will be unchanged

after this command is executed (see Transaction table on page 95).

4.9.4

Clear ECC status register transaction

The Clear ECC Status Register (CLECC_0_0) transaction resets bit ECSV[4] (2-bit ECC Detection), bit ECSV[3] (1-bit

ECC Correction), INSV[1:0] ECC detection status bits, Address Trap Register EATV[31:0], and ECC Detection

Counter ECTV[15:0]. It is not necessary to set the WRPGEN bit before this transaction is executed. The Clear ECC

Status Register transaction will be accepted even when the device remains busy with WRPGEN set to 1, as the

device does remain busy when either error bit is set. The WRPGEN bit will be unchanged after this command is

executed (see Transaction table on page 95).

4.9.5

Write any register transaction

The Write Any Register (WRARG_C_1 / WRARG_4_1) transaction provides a way to write any device register,

nonvolatile or volatile. The transaction includes the address of the register to be written, followed by one byte of

data to write in the addressed register (see Transaction table on page 95).

Before the WRARG_C_1 / WRARG_4_1 transaction can be accepted by the device, a Write Enable (WRENB_0_0)

transaction must be issued and decoded, which sets the Write/Program Enable bit (WRPGEN) in the Status

operation is completed. The PRGERR and ERSERR bits in STR1V[6:5] can be checked to determine if any error

occurred during the operation.

Some registers have a mixture of bit types and individual rules controlling which bits can be modified. Some bits

are read only, some are OTP, and some are designated Reserved (DNU).

Read only bits are never modified and the related bits in the WRARG_C_1 / WRARG_4_1 transaction data byte are

ignored without setting a program or erase error indication (PRGERR or ERSERR in STR1V[6:5]). Hence, the value

of these bits in the WRARG_C_1 / WRARG_4_1 data byte do not matter.

OTP bits can only be programmed to the level opposite of their default state. Writing of OTP bits back to their

default state is ignored and no error is set.

Nonvolatile bits which are changed by the WRARG_C_1 / WRARG_4_1 data require nonvolatile register write time

(tW) to be updated. The update process involves an erase and a program operation on the nonvolatile register

bits. If either the erase or program portion of the update fails, the related error bit and RDYBSY bit in STR1V will

be set to 1.

Status Register 1 can be repeatedly read (polled) to monitor the RDYBSY bit (STR1V[0]) and the error bits

(STR1V[6,5]) to determine when the register write is completed or failed. If there is a write failure, the CLPEF_0_0

transaction is used to clear the error status and enable the device to return to standby state.

The ASP PPB Lock Register (PPLV) register cannot be written by the WRARG_C_1 / WRARG_4_1 transaction. Only

the Write PPB Lock Bit (WRPLB_0_0) transaction can write the PPLV Register.

The Data Integrity Check Register cannot be written by the WRARG_C_1 / WRARG_4_1 transaction. The Data

Integrity Check Register is loaded by running the Data Integrity Check transaction (DICHK_4_1).

28HS01GTAM03 Datenblatt(PDF) 59 Page - Infineon Technologies AG

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