28HS01GTAM03 datasheet(9/138 Pages) INFINEON

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Datasheet

9 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Interface overview

The SEMPER™ Flash with Octal Interface family consists of multiple densities with, 1.8V and 3.0V core and I/O

voltage options.

The device control logic is subdivided into two parallel operating sections: the Host Interface Controller (HIC) and

the Embedded Algorithm Controller (EAC). The HIC monitors signal levels on the device inputs and drives outputs

as needed to complete read, program, and write data transfers with the host system. The HIC delivers data from

the currently entered address map on read transfers; places write transfer address and data information into the

EAC command memory, and notifies the EAC of power transition, and write transfers. The EAC interrogates the

command memory, after a program or write transfer, for legal command sequences and performs the related

Embedded Algorithms.

Changing the nonvolatile data in the memory array requires a sequence of operations that are part of embedded

algorithms (EA). The algorithms are managed entirely by the internal EAC. The main algorithms perform

programming and erase of the main flash array data. The host system writes command codes to the flash device.

The EAC receives the command, performs all the necessary steps to complete the transaction, and provides

status information during the progress of an EA.

In addition to the mandatory SPI signals CK, CS#, SI/DQ0, SO/DQ1, and DQ[7:2], the SEMPER™ Flash with Octal

Interface device also includes RESET#, DS and INT# signals. The RESET# transition from LOW to HIGH returns the

device to the default state that occurs after an internal power-on reset (POR). The Data Strobe (DS) is synchro-

nized with the output data during read transactions enabling host system to capture data at high clock frequency

operation. The INT# is an open-drain output that can provide an interrupt to the device master to indicate when

the device transitions from busy to ready at the end of a program or erase operation or to indicate the detection

of an error (ECC) during read.

Infineon® Endurance Flex architecture provides system designers the ability to customize the NOR Flash

endurance and retention for their specific application. The host defines partitions for high endurance or long

retention, providing up to 1+ million cycles or 25 years of data retention.

The SEMPERFlash with Octal interface device supports error detection and correction by generating an

embedded Hamming error correction code during memory array programming. This ECC code is then used for

single-bit and double-bit error detection and single-bit correction during read.

The SEMPER™ Flash with Octal Interface device has built-in diagnostic features providing the host system with

the device status.

• Program and Erase Operation: Reporting of program or erase success, failure and suspend status

• error detection and correction: 1-bit and/or 2-bit error status with address trapping and error count

• Data Integrity Check: Error detection over memory array contents

• Interface CRC: Error detection over device interface

• SafeBoot: Reporting of proper flash device initialization and configuration corruption recovery

• Sector Erase Status: Reporting of erase success or failure status per sector

• Sector Erase Counter: Counts the number of erase cycles per sector

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