28HS01GTAM03 datasheet(62/138 Pages) INFINEON

62 / 138 page

Datasheet

62 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.10.5

Program persistent protection bit (PPB)

The Program Persistent Protect Bit (PRPPB_4_0) transaction programs a bit in the PPB Register to protect the

sector of the provided address from being programed or erased (see Transaction table on page 95).

The PRGERR bit in STR1V[6] may be checked to determine if any error occurred during the operation. Program

PPB bit transaction will abort when trying to program the PPB bits protected by ASPPPB (ASPO[3]), ASPPRM

(ASPO[0]) and PPBLCK (PPLV[0]) bit.

4.10.6

Program related registers and transactions

4.11

Erase

There are erase transactions for erasing data bits to 1 (all bytes are FFh) for the Memory Array and Persistent

Protection Bits.

These erase transactions can use any of these three protocols:

• SPI interface with SDR (1S-1S-1S) protocol, transfers the one byte command one bit per CK rising edge

• Octal interface with SDR (8S-8S-8S) protocol, transfers the two byte command eight bits per CK rising edge

• Octalinterface with DDR(8D-8D-8D) protocol,transfersthe two byte command eight bits per CK rising and falling

edge

Before any erase transaction can be accepted by the device, a Write Enable (WRENB_0_0) transaction must be

issued and decoded by the device. Erase transactions can only be executed by the device if the Write/Program

Enable bit (WRPGEN) in the Status Register is set to ‘1’ to enable erase operations. When an erase transaction is

completed, the WRPGEN bit is reset to a ‘0’.

While the erase transaction is in progress, the Status Register 1 may be read to check the value of the Device

Ready/Busy (RDYBSY) bit. The RDYBSY bit is a ‘1’ during the self-timed erase transaction, and is a ‘0’ when it is

completed.

The ERSERR bit in STR1V[5] can be checked to determine if any error occurred during the erase transaction.

An erase transaction applied to a sector that has been Write Protected through the Block Protection bits or ASP,

will not be executed and will set the ERSERR status fail bit.

Erase transactions will be initiated when CS# is driven into the logic HIGH state.

When the device is shipped from the factory the default erase state is all bytes are FFh.

4.11.1

Erase 4KB sector transaction

The Erase 4KB Sector (ER004_4_0) transaction sets all the bits of a 4KB sector to 1 (all bytes are FFh) (see Trans-

action table on page 95).

This transaction is ignored when the device is configured for uniform sectors only (CFR3V[3] = 1). If the Erase

4KB sector transaction is issued to a non-4KB sector address, the device will abort the operation and will not set

the ERSERR status fail bit.

Table 33

Program Related Registers and Transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Status Register 1 (STR1N, STR1V)

(see Table 41 on page 76)

Write Enable (WRENB_0_0)

Configuration Register 5 (CFR5N, CRF5V)

(see Table 54 on page 85)

Program Page (PRPGE_4_1)

Advance Sector Protect Register (ASPO)

(see Table 61 on page 88)

Program Secure Silicon (PRSSR_4_1)

ASP PPB Lock (PPLV) (see Table 63 on page 89)

Program Persistent Protection Bit (PRPPB_4_0)

ECC Status Register (ECSV)

(see Table 58 on page 86)

Clear Program and Erase Failure Flags

(CLPEF_0_0)

Clear Program and Erase Failure Flags

(CLPEF_0_0)

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