28HS01GTAM03 datasheet(7/138 Pages) INFINEON

7 / 138 page

Datasheet

7 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Pinout and signal description

Table 1

Signal description

Symbol

Type

Mandatory /

optional

Description

CS#

Input

Mandatory

Chip Select (CS#). All bus transactions are initiated with a HIGH to LOW transition on CS# and

terminated with a LOW to HIGH transition on CS#. Driving CS# LOW enables the device, placing it in

the active mode. When CS# is driven HIGH, the device enters standby mode, unless an internal

embedded operation is in progress. All other input pins are ignored and the output pins are put in

high impedance state. On parts where the pin configuration offers a dedicated RESET# pin, it

remains active when CS# is HIGH.

Input

Mandatory

Clock (CK). Clock provides the timing of the serial interface. Transactions are latched on the rising

edge of the clock. In SDR protocol, command, address and data inputs are latched on the rising edge

of the clock, while data is output on the falling edge of the clock. In DDR protocol, command,

address and data inputs are latched on both edges of the clock, and data is output on both edges

of the clock.

Output

Mandatory

Read Data Strobe (DS). DS is used for data read operations only and indicates output data valid

for SDR/DDR modes. During a read transaction while CS# is LOW, DS toggles to synchronize data

output until CS# goes High.

DQ[7:0]

Input/Output

Mandatory

Serial Data (DQ[7:0]). Bidirectional signals that transfer command, address and data information.

Legacy (x1) SPI Interface: DQ[0] is an input (SI) and DQ[1] is an output (SO).

Octal (x8) Interface: DQ[7:0] are input and output.

RESET#

Input (weak

pull-up)

Optional

Hardware Reset (RESET#). When LOW, the device will self initialize and return to the array read

state. DS and DQ[7:0] are placed into the high impedance state when RESET# is LOW. RESET#

includes a weak pull-up, meaning, if RESET# is left unconnected it will be pulled up to the HIGH state

on its own.

INT#

Output

(Open Drain)

Optional

System Interrupt (INT#). When LOW, the device is indicating that an internal event has occurred.

This signal is intended to be used as a system level interrupt for the device to indicate that an

on-chip event has occurred. INT# is an open-drain output. The recommended pull-up resistor for

the INT# outputs is 5 k to 10 k.

VCC

Power supply

Mandatory

Core Power Supply

VCCQ

Power supply

Mandatory

Input / Output Power Supply

VSS

Ground

supply

Mandatory

Core Ground

VSSQ

Ground

supply

Mandatory

Input / Output Ground

DNU

Do Not Use.

Note

1. Flash memory devices in BGA packages can be damaged if exposed to ultrasonic cleaning methods. The package, data integrity, or both may be

compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

28HS01GTAM03 Datenblatt(PDF) 7 Page - Infineon Technologies AG

28HS01GTAM03 Datenblatt(HTML) 7 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL