28HS01GTAM03 datasheet(4/138 Pages) INFINEON

4 / 138 page

Datasheet

4 of 138

002-18216 Rev. *W

2022-01-18

128Mb/256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Table of contents

Features ...........................................................................................................................................1

Performance summary ......................................................................................................................2

Data integrity....................................................................................................................................3

Table of contents...............................................................................................................................4

1 Pinout and signal description...........................................................................................................6

2 Interface overview..........................................................................................................................8

2.1 General description ................................................................................................................................................8

2.2 Signal protocols ....................................................................................................................................................10

2.3 Transaction protocol ............................................................................................................................................11

2.4 Register naming convention ................................................................................................................................22

2.5 Transaction naming convention..........................................................................................................................22

3 Address space maps ......................................................................................................................23

3.1 SEMPER™ Flash memory array.............................................................................................................................23

3.2 ID address space ...................................................................................................................................................25

3.3 JEDEC JESD216 SFDP space.................................................................................................................................25

3.4 SSR address space ................................................................................................................................................25

3.5 Registers................................................................................................................................................................26

4 Features.......................................................................................................................................28

4.1 Error detection and correction.............................................................................................................................28

4.2 Infineon® Endurance Flex architecture (wear leveling) ......................................................................................32

4.3 Interface CRC.........................................................................................................................................................36

4.4 Data integrity CRC.................................................................................................................................................40

4.5 Data protection schemes .....................................................................................................................................41

4.6 SafeBoot................................................................................................................................................................50

4.7 AutoBoot ...............................................................................................................................................................54

4.8 Read transactions .................................................................................................................................................54

4.9 Write transactions.................................................................................................................................................58

4.10 Program...............................................................................................................................................................60

4.11 Erase ....................................................................................................................................................................62

4.12 Suspend and resume embedded operation......................................................................................................64

4.13 Reset ....................................................................................................................................................................67

4.14 Power modes ......................................................................................................................................................71

4.15 Power up and power down ................................................................................................................................72

5 Registers......................................................................................................................................75

5.1 Register naming convention ................................................................................................................................76

5.2 Status register 1 (STR1x).......................................................................................................................................76

5.3 Status register 2 (STR2x).......................................................................................................................................78

5.4 Configuration register 1 (CFR1x) ..........................................................................................................................79

5.5 Configuration register 2 (CFR2x) ..........................................................................................................................80

5.6 Configuration register 3 (CFR3x) ..........................................................................................................................82

5.7 Configuration register 4 (CFR4x) ..........................................................................................................................83

5.8 Configuration register 5 (CFR5x) ..........................................................................................................................85

5.9 Interface CRC enable register (ICEV) ....................................................................................................................85

5.10 Interface CRC check-value register (ICRV) .........................................................................................................85

5.11 Memory array data integrity check CRC register (DCRV) ..................................................................................86

5.12 ECC status register (ESCV) ..................................................................................................................................86

5.13 ECC address trap register (EATV) .......................................................................................................................87

5.14 ECC error detection count register (ECTV).........................................................................................................87

5.15 Advanced sector protection register (ASPO).....................................................................................................88

5.16 ASP password register (PWDO) ..........................................................................................................................89

5.17 ASP PPB lock register (PPLV)..............................................................................................................................89

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