28HS01GTAM03 datasheet(72/138 Pages) INFINEON

72 / 138 page

Datasheet

72 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.14.2.2

Exit DPD

Device leaves DPD mode in one of the following ways:

Exit DPD Mode upon Hardware Reset

When the device is in DPD and CFR4NV[2] = 0, a Hardware reset will return the device to Standby mode.

Exit DPD Mode upon CS# Pulse

Device exits DPD upon receipt of CS# pulse of width tCSDPD. The CS# should be driven HIGH after the pulse. HIGH

to LOW transition on CS# is required to start a transaction cycle after the DPD exit. It takes tEXTDPD to come out of

DPD mode. The device will not respond until after tEXTDPD.

Figure 62

Exit DPD mode

The device maintains its configuration during DPD, meaning the device exits DPD in the same state as it entered.

Registers such as the ECC Status, ECC Error Detection Counter, Address Trap, and Interrupt Status Registers will

be cleared.

4.14.2.3

DPD related registers and transactions

4.15

Power up and power down

The device must not be selected at power up or power down until VCC reaches the correct value as follows:

•VCC (min) at power up, and then for a further delay of tPU

•VSS at power down

Table 39

DPD related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Configuration Register 4 (CFR4N, CFR4V)

(see Table 52 on page 83)

Enter Deep Power Down Mode (ENDPD_0_0)

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