28HS01GTAM03 datasheet(71/138 Pages) INFINEON

71 / 138 page

Datasheet

71 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.14

Power modes

4.14.1

Active power and standby power modes

The device is enabled and in the Active Power mode when Chip Select (CS#) is LOW. When CS# is HIGH, the device

is disabled, but may still be in an Active Power mode until all program, erase, and write operations have

completed. The device then goes into the Standby Power mode, and power consumption drops to ISB. See

Table 83 for parameter specifications.

4.14.2

Deep power down (DPD) mode

Although the standby current during normal operation is relatively low, standby current can be further reduced

with the DPD mode. The lower power consumption makes the DPD mode especially useful for battery powered

applications.

4.14.2.1

Enter DPD

The device can enter DPD mode in two ways:

1. Enter DPD Mode using Transaction

2. Enter DPD Mode upon Power-up or Reset

Enter DPD Mode using the Enter Deep Power Down Mode Transaction

The DPD mode is enabled by sending the Enter Deep Power Down Mode Transaction (ENDPD_0_0) then waiting

for a delay of tENTDPD. The CS# pin must be driven HIGH after the command byte has been latched. If this is not

done, then the DPD transaction will not be executed. After CS# is driven HIGH, the power-down state will be

entered within the time duration of tENTDPD (see Table 85 for timing specifications) and power consumption

drops to IDPD. See Table 83 for parameter specifications.

DPD can only be entered from an idle state. The DPD transaction is accepted only while the device is not

performing an embedded algorithm as indicated by the Status Register 1 volatile, Device Ready/Busy Status Flag

(RDYBSY) bit being cleared to zero (STR1V[0] = RDYBSY = 0). It is not allowed to send any transaction to device

during tENTDPD time.

Enter DPD Mode upon Power-up or Reset

If the DPDPOR configuration bit is enabled (CFR4NV[2] = 1), the device will be in DPD mode after the completion

of Power-up, Hardware Reset or CS# Signaling Reset. During POR or Reset the CS# should follow the voltage

applied on VCC to enter DPD mode as shown in Figure 61. It is not allowed to send any transaction to device

during tENTDPD time.

Figure 61

Enter DPD mode upon power-up or reset

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