28HS01GTAM03 datasheet(73/138 Pages) INFINEON

73 / 138 page

Datasheet

73 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.15.1

Power up

The device ignores all transactions until a time delay of tPU has elapsed after the moment that VCC rises above

the minimum VCC threshold (see Figure 63). However, correct operation of the device is not guaranteed if VCC

returns below VCC (min) during tPU. No command should be sent to the device until the end of tPU.

The device draws IPOR current during tPU. After power up (tPU), the WRPGEN bit is reset and there is the option to

be in the DPD mode or Standby mode. The DPDPOR bit in Configuration Register 4 (CFR4N[2]) controls if the

device will be in DPD or Standby mode after the completion of POR (see Table 52). If the DPDPOR bit is enabled

(CFR4N[2] = 1) the device is in DPD mode after power up. A Hardware reset (RESET#) required to return the device

to Standby mode after POR.

Figure 63

Power up

4.15.2

Power down

During power down or voltage drops below VCC(cut-off), the voltage must drop below VCC(LOW) for a period of

tPD for the part to initialize correctly on power up (see Figure 64). If during a voltage drop the VCC stays above

VCC(cut-off) the part will stay initialized and will work correctly when VCC is again above VCC(min). In the event

POR did not complete correctly after power up, the assertion of the RESET# signal will restart the POR process.

Figure 64

Power down and voltage drop

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