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28HS01GTAM03 Datenblatt(PDF) 81 Page - Infineon Technologies AG

Teilenummer 28HS01GTAM03
Bauteilbeschribung  S256Mb/512Mb/1Gb SEMPER??Flash Octal interface, 1.8V/3.0V
PDF  138 Pages
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Hersteller  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

28HS01GTAM03 Datenblatt(HTML) 81 Page - Infineon Technologies AG

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002-18216 Rev. *W
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
Octal interface, 1.8V/3.0V
Registers
Table 49
Latency code (cycles) versus frequency[24, 25, 27]
Latency code
Number of cycles
(1-1-1 / 8-8-8)
SDR SPI read transactions (MHz)
(1S-1S-1S / 1S-1S-8S)
SDR octal read transactions
(MHz)
(8S-8S-8S)
DDR octal read transactions
(MHz)
(8D-8D-8D)
RDAY2_C_0
RDSSR_4_0
RDARG_C_0[26]
RDECC_4_0
RDPPB_4_0
RDAY1_4_0
RDSSR_4_0
RDARG_4_0[26]
RDECC_4_0
RDPPB_4_0
RDAY2_4_0
RDSSR_4_0
RDARG_4_0[26]
RDECC_4_0
RDPPB_4_0
0000
0 / 5
50
50
42
0001
1 / 6
68
64
57
0010
2 / 8
81
92
85
0011
3 / 10
93
121
107
0100
4 / 12
106
150
121
0101
5 / 14
118
166 (HL-T) / 178 (HS-T)
135
0110
6 / 16
131
200
150
0111
7 / 18
143
200
164
1000
8 / 20
156
200
166 (HL-T) / 178 (HS-T)
1001
9 / 22
166
200
192
1010
10 / 23
166
200
200
1011
11 / 24
166
200
200
1100
12 / 25
166
200
200
1101
13 / 26
166
200
200
1110
14 / 27
166
200
200
1111
15 / 28
166
200
200
Notes
24. When using the ECC error reporting mechanisms, the read output data must be at least 2 bytes for correct ECC reporting.
25. CK frequency > 200MHz SDR, or > 200MHz DDR is not supported by HS-T family of devices and CK frequency > 166MHz SDR, or > 166MHz DDR is not
supported by HL-T family of devices.
26. RDARG_C_0 and RDARG_4_0 uses these latency cycles for reading nonvolatile registers.
27. RSFDP_3_0 always have a dummy cycle of eight and the maximum frequencies for different interfaces related to eight dummy cycles.



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