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28HS01GTAM03 Datenblatt(PDF) 99 Page - Infineon Technologies AG

Teilenummer 28HS01GTAM03
Bauteilbeschribung  S256Mb/512Mb/1Gb SEMPER??Flash Octal interface, 1.8V/3.0V
PDF  138 Pages
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Hersteller  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

28HS01GTAM03 Datenblatt(HTML) 99 Page - Infineon Technologies AG

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6.4
Octal (8S-8S-8S, 8D-8D-8D) transaction table
Table 78
Octal (8S-8S-8S, 8D-8D-8D) transaction table
Read
device ID
RDIDN_4_0
Read manufacturer and
device identification trans-
action provides read access
to manufacturer and device
identification.
-
9F
(CMD)
9F
(CMD)
00
(ADDR)
00
(ADDR)
00
(ADDR)
00
(ADDR)
--
-
-
-
-
-
-
Figure 27/
Figure 28
166/200
4
RSFDP_4_0
Read JEDEC Serial Flash
Discoverable Parameters
transaction sequentially
accesses the Serial Flash
Discovery Parameters (SFDP).
-
5A
(CMD)
5A
(CMD)
ADDR
[31:24]
ADDR
[23:16]
ADDR
[15:8]
ADDR
[7:0]
--
-
-
-
-
-
-
92 (SDR) /
85 (DDR)
RDUID_4_0
Read Unique ID accesses a
factory programmed 64-bit
number which is unique to
each device.
-
4C
(CMD)
4C
(CMD)
00
(ADDR)
00
(ADDR)
00
(ADDR)
00
(ADDR)
--
-
-
-
-
-
-
166 / 200
Register
access
RDSR1_4_0
Read Status Register 1 trans-
action allows the Status
Register 1 contents to be read
from DQ[7:0]
-
05
(CMD)
05
(CMD)
00
(ADDR)
00
(ADDR)
00
(ADDR)
00
(ADDR)
--
-
-
-
-
-
-
Figure 27/
Figure 29
RDSR2_4_0
Read Status Register-2
transaction allows the Status
Register-2 contents to be read
from DQ[7:0]
-
07
(CMD)
07
(CMD)
00
(ADDR)
00
(ADDR)
00
(ADDR)
00
(ADDR)
--
-
-
-
-
-
-
RDARG_4_0
Read Any Register trans-
action provides a way to read
all addressed nonvolatile and
volatile device registers.
-
65
(CMD)
65
(CMD)
ADDR
[31:24]
ADDR
[23:16]
ADDR
[15:8]
ADDR
[7:0]
--
-
-
-
-
-
-
Figure 27/
Figure 28
WRENB_0_0
Write Enable sets the Write
Enable Latch bit of the Status
Register 1 to 1 to enable write,
program and erase transac-
tions.
-
06
(CMD)
06
(CMD)
--
-
-
-
-
-
-
-
-
-
-
Figure 18/
Figure 19
N/A
WRDIS_0_0
Write Disable sets the Write
Enable Latch bit of the Status
Register 1 to 0 to disable
write, program and erase
transactions execution.
-
04
(CMD)
04
(CMD)
--
-
-
-
-
-
-
-
-
-
-
WRARG_4_1
Write Any Register trans-
action provides a way to write
all addressed nonvolatile and
volatile device registers.
WRENB_
0_0
71
(CMD)
71
(CMD)
ADDR
[31:24]
ADDR
[23:16]
ADDR
[15:8]
ADDR
[7:0]
Input
Data
[7:0]
--
-
-
-
-
-
Figure 24/
Figure 25
4
Note
32. In case of Octal DDR protocol.



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