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28HS01GTAM03 Datenblatt(PDF) 49 Page - Infineon Technologies AG

Teilenummer 28HS01GTAM03
Bauteilbeschribung  S256Mb/512Mb/1Gb SEMPER??Flash Octal interface, 1.8V/3.0V
PDF  138 Pages
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Hersteller  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

28HS01GTAM03 Datenblatt(HTML) 49 Page - Infineon Technologies AG

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002-18216 Rev. *W
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
Octal interface, 1.8V/3.0V
Features
4.5.2.9
General ASP guidelines
• Persistent protection (ASPPER) and Password protection (ASPPWD) are mutually exclusive - only one option
can be programmed.
• Read Password protection (ASPRDP) if desired, must be programmed at the same time as Password protection
(ASPPWD).
• Once the password is programmed and verified, the Password Protection scheme (ASPPWD) must be
programmed (to 0) to prevent reading the password.
• When the Read Password scheme and Password Protection scheme are enabled (i.e. ASPO[5] - ASPRDP, ASPO[2]
- ASPPWD are programmed to 0), then all addresses are redirected to the Boot Sector until the password
unlocking sequence is properly entered with the correct password. At which time, the Read Password Mode is
disabled and all addressing will select the proper location.
• Programming memory spaces or writing registers is not allowed when Read Password Protection Mode is active.
4.5.2.10
ASP related registers and transactions
4.5.3
Secure silicon region (SSR)
Secure silicon region is a 1024 byte memory region (separate from the main memory array). The 1024 bytes are
divided into 32, individually lockable 32-byte regions. Figure 51 provides an overview of SSR.
Figure 51
OTP protection (Nonvolatile)
Table 20
ASP related registers and transactions
Related registers
Related SPI transactions
(see Table 75 on page 95)
Related octal transactions
(see Table 78 on page 99)
Advanced Sector Protection Register (ASPO)
(see Table 61 on page 88)
Read Dynamic Protection Bit (RDDYB_4_0)
Read Dynamic Protection Bit (RDDYB_4_0)
Configuration Register 1 (CFR1N, CFR1V)
(see Table 45 on page 79)
Write Dynamic Protection Bit (WRDYB_4_1)
Write Dynamic Protection Bit (WRDYB_4_1)
Read Persistent Protection Bit (RDPPB_4_0)
Read Persistent Protection Bit (RDPPB_4_0)
Program Persistent Protection Bit (PRPPB_4_0)
Program Persistent Protection Bit (PRPPB_4_0)
Erase Persistent Protection Bit (ERPPB_0_0)
Erase Persistent Protection Bit (ERPPB_0_0)
Write PPB Protection Lock Bit (WRPLB_0_0)
Write PPB Protection Lock Bit (WRPLB_0_0)
Read Password Protection Mode Lock Bit
(RDPLB_0_0)
Read Password Protection Mode Lock Bit
(RDPLB_4_0)
Password Unlock (PWDUL_0_1)
Password Unlock (PWDUL_4_1)
Write Enable (WRENB_0_0)
Write Enable (WRENB_0_0)
Read Any Register (RDARG_C_0)
Read Any Register (RDARG_4_0)
Write Any Register (WRARG_C_1)
Write Any Register (WRARG_4_1)



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