28HS01GTAM03 datasheet(82/138 Pages) INFINEON

82 / 138 page

Datasheet

82 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Registers

5.6

Configuration register 3 (CFR3x)

Configuration Register 3 controls transaction behavior.

Table 50

Configuration register 3

Bit

number

Name

Function

Read/Write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

CFR3N[7:6]

CFR3V[7:6]

VRGLAT[1:0]

Volatile Register Read

Latency selection -

Dummy cycles

required for initial

data access

N -> R/W

V -> R/W

Description: The VRGLAT[1:0] bits control the read latency (dummy

cycles) delay in all variable latency register read transactions.

VRGLAT[1:0] selection allows the user to adjust the read latency during

normal operation based on different operating frequencies.

Selection Options:

00, 01, 10, 11 Latency Cycles Selection based on transaction opcodes

Dependency: N/A

CFR3N[5]

CFR3V[5]

BLKCHK

Blank Check selection

during Erase

operation for better

endurance

N -> R/W

V -> R/W

Description: When this feature is enabled an erase transaction first

evaluates the erase status of the sector. If the sector is found to erased,

the erase operation is aborted. In other words, the erase operation is

only executed if programmed bits are found in the sector. Disabling

BLKCHK executes an erase operation unconditionally.

Selection Options:

0 = Blank Check is disabled before executing an erase operation

1 = Blank Check evaluation is enabled before executing an erase

operation

Dependency: N/A

CFR3N[4]

CFR3V[4]

PGMBUF

Program Buffer Size

selection

N -> R/W

V -> R/W

Description: The PGMBUF bit selects the Programming Buffer size

which is used for page programming. Program buffer size affects the

device programming time.

Note If programming data exceeds the program buffer size, data gets

wrapped.

Selection Options:

0 = 256 Byte Write Buffer Size

1 = 512 Byte Write Buffer Size

Dependency: N/A

CFR3N[3]

CFR3V[3]

UNHYSA

Uniform or Hybrid

Sector Architecture

Selection

N -> R/W

V -> R

Description: The UNHYSA bit selects between uniform (all 256KB

sectors) or hybrid (4KB sectors and 256KB sectors) sector architecture.

If hybrid sector architecture is selected, 4KB sector block is made part

of the main Flash array address map. The 4KB sector block can overlay

at either the highest or the lowest address range of the device. If

uniform sector architecture is selected, 4KB sector block is removed

from the address map and all sectors are of uniform size.

Note Hybrid sector architecture also enables 4KB Sector Erase trans-

action (20h). Otherwise, 4KB Sector Erase transaction, if issued, is

ignored by the device.

Selection Options:

0 = Hybrid Sector Architecture (combination of 4KB sectors and 256KB

sectors)

1 = Uniform Sector Architecture (all 256KB sectors)

Dependency: SP4KBS(CFR1N[6]), TB4KBS(CFR1N[2])

CFR3N[2]

CFR3V[2]

RESRVD

Reserved for Future

Use

N -> R/W

V -> R/W

This bit is Reserved for future use. This bit must always be

written/loaded to its default state.

CFR3N[1]

CFR3V[1]

RESRVD

Reserved for Future

Use

N -> R/W

V -> R/W

CFR3N[0]

CFR3V[0]

RESRVD

Reserved for Future

Use

N -> R/W

V -> R/W

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